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Diffstat (limited to 'src/main/scala/chisel3/util/Valid.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 0229b7f8..0bfe7cb3 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -6,6 +6,8 @@ package chisel3.util import chisel3._ +import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order + // TODO: remove this once we have CompileOptions threaded through the macro system. import chisel3.core.ExplicitCompileOptions.NotStrict @@ -34,6 +36,7 @@ object Valid { */ object Pipe { + @chiselName def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = { if (latency == 0) { val out = Wire(Valid(enqBits)) |