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authorducky2017-02-01 16:07:09 -0800
committerRichard Lin2017-02-07 16:24:17 -0800
commit8d2fff4eff3ba0f92437b290985b35afbb0ed565 (patch)
tree97b3f62d73c61ceb12ccb6bd684e63df5be8ed0d /src/main/scala/chisel3/util/Valid.scala
parentad20406f301e04075e051147092cf9c12a6a6ca8 (diff)
Name all the things
Diffstat (limited to 'src/main/scala/chisel3/util/Valid.scala')
-rw-r--r--src/main/scala/chisel3/util/Valid.scala3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 0229b7f8..0bfe7cb3 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -6,6 +6,8 @@
package chisel3.util
import chisel3._
+import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
+
// TODO: remove this once we have CompileOptions threaded through the macro system.
import chisel3.core.ExplicitCompileOptions.NotStrict
@@ -34,6 +36,7 @@ object Valid {
*/
object Pipe
{
+ @chiselName
def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = {
if (latency == 0) {
val out = Wire(Valid(enqBits))