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-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 3d10670e..3409ce94 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -2,7 +2,7 @@
package chisel3.internal.firrtl
import chisel3._
-import chisel3.experimental._
+import chisel3.experimental.{Interval, _}
import chisel3.internal.BaseBlackBox
private[chisel3] object Emitter {
@@ -33,6 +33,12 @@ private class Emitter(circuit: Circuit) {
case d: UInt => s"UInt${d.width}"
case d: SInt => s"SInt${d.width}"
case d: FixedPoint => s"Fixed${d.width}${d.binaryPoint}"
+ case d: Interval =>
+ val binaryPointString = d.binaryPoint match {
+ case UnknownBinaryPoint => ""
+ case KnownBinaryPoint(value) => s".$value"
+ }
+ d.toType
case d: Analog => s"Analog${d.width}"
case d: Vec[_] => s"${emitType(d.sample_element, clearDir)}[${d.length}]"
case d: Record => {