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Diffstat (limited to 'src/main/scala/chisel3/Driver.scala')
| -rw-r--r-- | src/main/scala/chisel3/Driver.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index a0713379..11a447d1 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -95,7 +95,7 @@ trait BackendCompilationUtilities { /** Generates a Verilator invocation to convert Verilog sources to C++ * simulation sources. * - * The Verilator prefix will be V$dutFile, and running this will generate + * The Verilator prefix will be V\$dutFile, and running this will generate * C++ sources and headers as well as a makefile to compile them. * * @param dutFile name of the DUT .v without the .v extension |