diff options
Diffstat (limited to 'src/main/scala/Chisel/testers')
| -rw-r--r-- | src/main/scala/Chisel/testers/BasicTester.scala | 8 | ||||
| -rw-r--r-- | src/main/scala/Chisel/testers/TesterDriver.scala | 2 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/Chisel/testers/BasicTester.scala index d3e9e7c8..b8c1494a 100644 --- a/src/main/scala/Chisel/testers/BasicTester.scala +++ b/src/main/scala/Chisel/testers/BasicTester.scala @@ -3,9 +3,12 @@ package Chisel.testers import Chisel._ +import scala.language.experimental.macros + import internal._ import internal.Builder.pushCommand import internal.firrtl._ +import internal.sourceinfo.SourceInfo class BasicTester extends Module { // The testbench has no IOs, rather it should communicate using printf, assert, and stop. @@ -19,9 +22,10 @@ class BasicTester extends Module { * reset). If your definition of reset is not the encapsulating Module's * reset, you will need to gate this externally. */ - def stop() { + def stop()(implicit sourceInfo: SourceInfo) { + // TODO: rewrite this using library-style SourceInfo passing. when (!reset) { - pushCommand(Stop(Node(clock), 0)) + pushCommand(Stop(sourceInfo, Node(clock), 0)) } } diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala index c0cdfb3f..a56bb8b7 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/Chisel/testers/TesterDriver.scala @@ -47,7 +47,7 @@ object TesterDriver extends BackendCompilationUtilities { // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe if ((firrtlToVerilog(target, path) #&& - verilogToCpp(target, path, additionalVFiles, cppHarness) #&& + verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& cppToExe(target, path)).! == 0) { executeExpectingSuccess(target, path) } else { |