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Diffstat (limited to 'src/main/scala/Chisel/Bits.scala')
| -rw-r--r-- | src/main/scala/Chisel/Bits.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala index 209dbd1f..021532a1 100644 --- a/src/main/scala/Chisel/Bits.scala +++ b/src/main/scala/Chisel/Bits.scala @@ -175,7 +175,10 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: * * The width of the output is sum of the inputs. Generates no logic. */ - def ## (other: Bits): UInt = Cat(this, other) + def ## (other: Bits): UInt = { + val w = this.width + other.width + pushOp(DefPrim(UInt(w), ConcatOp, this.ref, other.ref)) + } @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3") override def toBits: UInt = asUInt |