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Diffstat (limited to 'docs/src/cookbooks/verilog-vs-chisel.md')
| -rw-r--r-- | docs/src/cookbooks/verilog-vs-chisel.md | 1 |
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diff --git a/docs/src/cookbooks/verilog-vs-chisel.md b/docs/src/cookbooks/verilog-vs-chisel.md index 1adf609e..75cc0ec8 100644 --- a/docs/src/cookbooks/verilog-vs-chisel.md +++ b/docs/src/cookbooks/verilog-vs-chisel.md @@ -15,7 +15,6 @@ This page serves as a quick introduction to Chisel for those familiar with Veril import chisel3._ import chisel3.util.{switch, is} import chisel3.stage.ChiselStage -import chisel3.experimental.ChiselEnum import chisel3.util.{Cat, Fill, DecoupledIO} ``` |