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| author | Jack | 2023-01-12 06:11:50 +0000 |
|---|---|---|
| committer | Jack | 2023-01-12 06:11:50 +0000 |
| commit | 8ba5f8d5011df70e817d3011ea4afd6976df243e (patch) | |
| tree | 5899c699e5164588c40aa7c3a7c5e62b79d7b804 /docs/src/cookbooks/verilog-vs-chisel.md | |
| parent | 5aa60ecda6bd2b02dfc7253a47e53c7647981a5c (diff) | |
| parent | 6a63353f2a6c3311e61b9a7b5b899d8ad904a86d (diff) | |
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'docs/src/cookbooks/verilog-vs-chisel.md')
| -rw-r--r-- | docs/src/cookbooks/verilog-vs-chisel.md | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/docs/src/cookbooks/verilog-vs-chisel.md b/docs/src/cookbooks/verilog-vs-chisel.md index 1adf609e..75cc0ec8 100644 --- a/docs/src/cookbooks/verilog-vs-chisel.md +++ b/docs/src/cookbooks/verilog-vs-chisel.md @@ -15,7 +15,6 @@ This page serves as a quick introduction to Chisel for those familiar with Veril import chisel3._ import chisel3.util.{switch, is} import chisel3.stage.ChiselStage -import chisel3.experimental.ChiselEnum import chisel3.util.{Cat, Fill, DecoupledIO} ``` |