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-rw-r--r--core/src/main/scala/chisel3/internal/BiConnect.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala
index fcea4fe2..aa7d7ac3 100644
--- a/core/src/main/scala/chisel3/internal/BiConnect.scala
+++ b/core/src/main/scala/chisel3/internal/BiConnect.scala
@@ -120,9 +120,10 @@ private[chisel3] object BiConnect {
if (notStrict) {
// chisel3 <> is commutative but FIRRTL <- is not
val flipped = {
+ import ActualDirection._
// Everything is flipped when it's the port of a child
val childPort = left_r._parent.get != context_mod
- val isFlipped = left_r.direction == ActualDirection.Bidirectional(ActualDirection.Flipped)
+ val isFlipped = Seq(Bidirectional(Flipped), Input).contains(left_r.direction)
isFlipped ^ childPort
}
val (newLeft, newRight) = if (flipped) pair.swap else pair