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-rw-r--r--core/src/main/scala/chisel3/SIntFactory.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala
index b34c7dde..3fafacda 100644
--- a/core/src/main/scala/chisel3/SIntFactory.scala
+++ b/core/src/main/scala/chisel3/SIntFactory.scala
@@ -5,8 +5,10 @@ package chisel3
import chisel3.internal.firrtl.{IntervalRange, SLit, Width}
trait SIntFactory {
+
/** Create an SInt type with inferred width. */
def apply(): SInt = apply(Width())
+
/** Create a SInt type or port with fixed width. */
def apply(width: Width): SInt = new SInt(width)