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authorJack Koenig2022-01-10 10:39:52 -0800
committerJack Koenig2022-01-10 15:53:55 -0800
commit3131c0daad41dea78bede4517669e376c41a325a (patch)
tree55baed78a6a01f80ff3952a08233ca553a19964f /core/src/main/scala/chisel3/SIntFactory.scala
parentdd36f97a82746cec0b25b94651581fe799e24579 (diff)
Apply scalafmt
Command: sbt scalafmtAll
Diffstat (limited to 'core/src/main/scala/chisel3/SIntFactory.scala')
-rw-r--r--core/src/main/scala/chisel3/SIntFactory.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala
index b34c7dde..3fafacda 100644
--- a/core/src/main/scala/chisel3/SIntFactory.scala
+++ b/core/src/main/scala/chisel3/SIntFactory.scala
@@ -5,8 +5,10 @@ package chisel3
import chisel3.internal.firrtl.{IntervalRange, SLit, Width}
trait SIntFactory {
+
/** Create an SInt type with inferred width. */
def apply(): SInt = apply(Width())
+
/** Create a SInt type or port with fixed width. */
def apply(width: Width): SInt = new SInt(width)