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Diffstat (limited to 'core/src/main/scala/chisel3/Data.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/Data.scala | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index 0832161e..5513035b 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -156,7 +156,9 @@ package experimental { // with compiled artifacts (vs. elaboration-time reflection)? def modulePorts(target: BaseModule): Seq[(String, Data)] = target.getChiselPorts - // Returns all module ports with underscore-qualified names + /** Returns all module ports with underscore-qualified names + * return includes [[Module.clock]] and [[Module.reset]] + */ def fullModulePorts(target: BaseModule): Seq[(String, Data)] = { def getPortNames(name: String, data: Data): Seq[(String, Data)] = Seq(name -> data) ++ (data match { case _: Element => Seq() |