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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/UserModule.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
index 8b176c3b..218b27c6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
@@ -88,8 +88,8 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions)
abstract class ImplicitModule(implicit moduleCompileOptions: CompileOptions)
extends UserModule {
// Implicit clock and reset pins
- val clock = IO(Input(Clock()))
- val reset = IO(Input(Bool()))
+ val clock: Clock = IO(Input(Clock()))
+ val reset: Reset = IO(Input(Bool()))
// Setup ClockAndReset
Builder.currentClockAndReset = Some(ClockAndReset(clock, reset))