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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index f4b36888..55ef7491 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -9,7 +9,7 @@ import chisel3.internal.Builder._
import chisel3.internal.firrtl._
import chisel3.internal.firrtl.{Command => _, _}
import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
-import chisel3.ImplicitCompileOptions
+//import chisel3.CompileOptions
object Module {
/** A wrapper method that all Module instantiations must be wrapped in
@@ -51,7 +51,7 @@ object Module {
*/
abstract class Module(
override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
- (implicit moduleCompileOptions: ImplicitCompileOptions)
+ (implicit moduleCompileOptions: CompileOptions)
extends HasId {
// _clock and _reset can be clock and reset in these 2ary constructors
// once chisel2 compatibility issues are resolved