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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 95ad95ef..4240a945 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -73,6 +73,7 @@ object BiConnect {
if(left_v.length != right_v.length) { throw MismatchedVecException }
for(idx <- 0 until left_v.length) {
try {
+ implicit val compileOptions = connectCompileOptions
connect(sourceInfo, connectCompileOptions, left_v(idx), right_v(idx), context_mod)
} catch {
case BiConnectException(message) => throw BiConnectException(s"($idx)$message")