diff options
| -rw-r--r-- | core/src/main/scala/chisel3/Reg.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala index b2b99cc1..bd9e5311 100644 --- a/core/src/main/scala/chisel3/Reg.scala +++ b/core/src/main/scala/chisel3/Reg.scala @@ -127,7 +127,7 @@ object RegNext { * val x = Wire(UInt()) * val y = Wire(UInt(8.W)) * val r1 = RegInit(x) // width will be inferred - * val r2 = RegInit(y) // width is set to 8 + * val r2 = RegInit(y) // width will be inferred * }}} * * 3. [[Aggregate]] initializer - width will be set to match the aggregate |