diff options
| author | Jack Koenig | 2021-01-26 17:15:57 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-27 01:15:57 +0000 |
| commit | d0db0b8b4661e64a79e8b14a24a4fa1baace1c3d (patch) | |
| tree | b426b015d0967f40f911e4f87a66dbee201ffb53 | |
| parent | 2a96767097264eade18ff26e1d8bce192383a190 (diff) | |
Fix incorrect comment in ScalaDoc (#1756)
| -rw-r--r-- | core/src/main/scala/chisel3/Reg.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala index b2b99cc1..bd9e5311 100644 --- a/core/src/main/scala/chisel3/Reg.scala +++ b/core/src/main/scala/chisel3/Reg.scala @@ -127,7 +127,7 @@ object RegNext { * val x = Wire(UInt()) * val y = Wire(UInt(8.W)) * val r1 = RegInit(x) // width will be inferred - * val r2 = RegInit(y) // width is set to 8 + * val r2 = RegInit(y) // width will be inferred * }}} * * 3. [[Aggregate]] initializer - width will be set to match the aggregate |