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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala5
-rw-r--r--src/test/scala/chiselTests/Vec.scala5
2 files changed, 7 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index be874042..8143d4db 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -24,13 +24,13 @@ sealed abstract class Aggregate extends Data {
pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = {
- SeqUtils.do_asUInt(getElements.map(_.asUInt()))
+ SeqUtils.do_asUInt(flatten.map(_.asUInt()))
}
private[core] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
compileOptions: CompileOptions): Unit = {
var i = 0
val bits = Wire(UInt(this.width), init=that) // handles width padding
- for (x <- getElements) {
+ for (x <- flatten) {
x.connectFromBits(bits(i + x.getWidth - 1, i))
i += x.getWidth
}
@@ -501,7 +501,6 @@ class Bundle extends Record {
* be one, otherwise returns None.
*/
private def getBundleField(m: java.lang.reflect.Method): Option[Data] = m.invoke(this) match {
- case v: Vec[_] if v.isEmpty => None
case d: Data => Some(d)
case Some(d: Data) => Some(d)
case _ => None
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 2ece7c88..df2d6ec0 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -144,6 +144,11 @@ class ZeroEntryVecTester extends BasicTester {
require(0.U.asTypeOf(bundleWithZeroEntryVec).getWidth == 1)
require(bundleWithZeroEntryVec.asUInt.getWidth == 1)
+ val m = Module(new Module {
+ val io = IO(Output(bundleWithZeroEntryVec.cloneType))
+ })
+ Wire(init = m.io.bar)
+
stop()
}