diff options
| -rw-r--r-- | src/main/scala/Core.scala | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/main/scala/Core.scala b/src/main/scala/Core.scala index a5caa9aa..8dd60bb8 100644 --- a/src/main/scala/Core.scala +++ b/src/main/scala/Core.scala @@ -1137,6 +1137,11 @@ abstract class Module(private[Chisel] _reset: Bool = null) extends Id { } } +// TODO: actually implement BlackBox (this hack just allows them to compile) +abstract class BlackBox(private[Chisel] _reset: Bool = null) extends Module(_reset) { + def setVerilogParameters(s: String): Unit = {} +} + object when { def execBlock(block: => Unit): Command = { pushScope |