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authorJim Lawson2015-07-17 15:11:08 -0700
committerJim Lawson2015-07-17 15:11:08 -0700
commitb6332bdd784be50215a85c948d2553c5119ffb90 (patch)
tree9d72cba7f53dcdaa743b1b3c2bd18dbfe8c4db63 /src
parentbdadf13bd0a31c6e3d8cb37b7d117250db80484d (diff)
Reverse list (from bit 0 - little endian to MSB - big endian).
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/Core.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Core.scala b/src/main/scala/Core.scala
index 28a76663..3385f629 100644
--- a/src/main/scala/Core.scala
+++ b/src/main/scala/Core.scala
@@ -346,7 +346,7 @@ abstract class Data(dirArg: Direction) extends Id {
wire.asInstanceOf[this.type]
}
def toBits: UInt = {
- val elts = this.flatten
+ val elts = this.flatten.reverse
Cat(elts.head, elts.tail:_*).asUInt
}
def makeLit(value: BigInt, width: Int): this.type = {