From b6332bdd784be50215a85c948d2553c5119ffb90 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 17 Jul 2015 15:11:08 -0700
Subject: Reverse list (from bit 0 - little endian to MSB - big endian).

---
 src/main/scala/Core.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/Core.scala b/src/main/scala/Core.scala
index 28a76663..3385f629 100644
--- a/src/main/scala/Core.scala
+++ b/src/main/scala/Core.scala
@@ -346,7 +346,7 @@ abstract class Data(dirArg: Direction) extends Id {
     wire.asInstanceOf[this.type]
   }
   def toBits: UInt = {
-    val elts = this.flatten
+    val elts = this.flatten.reverse
     Cat(elts.head, elts.tail:_*).asUInt
   }
   def makeLit(value: BigInt, width: Int): this.type = {
-- 
cgit v1.2.3