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authorAndrew Waterman2015-07-30 17:42:25 -0700
committerAndrew Waterman2015-07-30 17:42:25 -0700
commita3cd76901958ee88da2b56d67ce0dee263d3301c (patch)
treed9124affe1254d914c2418590ac953ad295bca74 /src
parent1a53cb9c9b76d45b8b809ac0f65a5e08507072d6 (diff)
Correct implementation of andR
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/Chisel/Core.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index d054c10f..27d07e30 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -668,8 +668,8 @@ sealed abstract class Bits(dirArg: Direction, width: Int, lit: Option[LitArg]) e
d
}
- def orR = !(this === Bits(0))
- def andR = (this === Bits(-1))
+ def orR = this != Bits(0)
+ def andR = ~this === Bits(0)
def xorR = bits_redop(XorReduceOp)
def toBools: Vec[Bool] = Vec.tabulate(this.getWidth)(i => this(i))