diff options
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index d054c10f..27d07e30 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -668,8 +668,8 @@ sealed abstract class Bits(dirArg: Direction, width: Int, lit: Option[LitArg]) e d } - def orR = !(this === Bits(0)) - def andR = (this === Bits(-1)) + def orR = this != Bits(0) + def andR = ~this === Bits(0) def xorR = bits_redop(XorReduceOp) def toBools: Vec[Bool] = Vec.tabulate(this.getWidth)(i => this(i)) |