diff options
| author | Schuyler Eldridge | 2019-08-08 18:53:02 -0400 |
|---|---|---|
| committer | GitHub | 2019-08-08 18:53:02 -0400 |
| commit | 87a57551771eca26159d79f48f2b57005ff69c7c (patch) | |
| tree | 8c37e85d17ed616df9bb454b7dd39e5b3bd14922 /src | |
| parent | 59d72b37d38556b7d11e55c44057d01e07fe1e31 (diff) | |
| parent | 9e99adbe920f3127e02a8dac05c972e3ea518c12 (diff) | |
Merge pull request #1148 from freechipsproject/vec-vec-chisel-type-message
Require target is hardware for Vec.apply(a: UInt)
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 0884ad37..2f67f375 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -272,4 +272,15 @@ class VecSpec extends ChiselPropSpec { io.out := VecInit(Seq(4.U, 5.U, DontCare, 2.U)) }) } + + property("Indexing a Chisel type Vec by a hardware type should give a sane error message") { + assertThrows[ExpectedHardwareException] { + elaborate{ + new Module { + val io = IO(new Bundle{}) + val foo = Vec(2, Bool()) + foo(0.U) := false.B + }} + } + } } |
