diff options
| author | ducky | 2016-11-18 12:50:35 -0800 |
|---|---|---|
| committer | ducky | 2016-11-21 13:32:47 -0800 |
| commit | 6b7acc715010b14c22e15f5084efb11862151a47 (patch) | |
| tree | d958476e009f607262f7ca49045d0df8f20027e6 /src | |
| parent | 75da1093142b57a58d61fe5e57181041bc59146d (diff) | |
Fix Log2
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/util/CircuitMath.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala index 83e5feb1..a422b5fe 100644 --- a/src/main/scala/chisel3/util/CircuitMath.scala +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -18,7 +18,7 @@ object Log2 { } else if (width == 2) { x(1) } else if (width <= divideAndConquerThreshold) { - Mux(x(width-1), UInt((width-1).W), apply(x, width-1)) + Mux(x(width-1), (width-1).asUInt, apply(x, width-1)) } else { val mid = 1 << (log2Ceil(width) - 1) val hi = x(width-1, mid) |
