From 6b7acc715010b14c22e15f5084efb11862151a47 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 12:50:35 -0800
Subject: Fix Log2

---
 src/main/scala/chisel3/util/CircuitMath.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 83e5feb1..a422b5fe 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -18,7 +18,7 @@ object Log2 {
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt((width-1).W), apply(x, width-1))
+      Mux(x(width-1), (width-1).asUInt, apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
-- 
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