Incorporate chisel3-tests; update Makefile.

26 files changed, 1063 insertions, 0 deletions

diff --git a/src/test/scala/ChiselTests/BitsOps.scala b/src/test/scala/ChiselTests/BitsOps.scala
new file mode 100644
index 00000000..bfcbaf49
--- /dev/null
+++ b/src/test/scala/ChiselTests/BitsOps.scala
@@ -0,0 +1,33 @@
+package ChiselTests
+import Chisel._
+
+class BitsOps extends Module {
+  val io = new Bundle {
+    val a = Bits(INPUT, 16)
+    val b = Bits(INPUT, 16)
+    val notout = Bits(OUTPUT, 16)
+    val andout = Bits(OUTPUT, 16)
+    val orout = Bits(OUTPUT, 16)
+    val xorout = Bits(OUTPUT, 16)
+  }
+
+  io.notout := ~io.a
+  io.andout := io.a & io.b
+  io.orout := io.a | io.b
+  io.xorout := io.a ^ io.b
+}
+
+class BitsOpsTester(c: BitsOps) extends Tester(c) {
+  val mask = (1 << 16)-1;
+  for (t <- 0 until 16) {
+    val test_a = rnd.nextInt(1 << 16)
+    val test_b = rnd.nextInt(1 << 16)
+    poke(c.io.a, test_a)
+    poke(c.io.b, test_b)
+    step(1)
+    expect(c.io.notout, mask & (~test_a))
+    expect(c.io.andout, mask & (test_a & test_b))
+    expect(c.io.orout,  mask & (test_a | test_b))
+    expect(c.io.xorout, mask & (test_a ^ test_b))
+  }
+}
diff --git a/src/test/scala/ChiselTests/BundleWire.scala b/src/test/scala/ChiselTests/BundleWire.scala
new file mode 100644
index 00000000..50bb60e2
--- /dev/null
+++ b/src/test/scala/ChiselTests/BundleWire.scala
@@ -0,0 +1,34 @@
+package ChiselTests
+import Chisel._
+
+class Coord extends Bundle {
+  val x = UInt(width = 32)
+  val y = UInt(width = 32)
+}
+
+class BundleWire extends Module {
+  val io = new Bundle {
+    val in   = (new Coord).asInput
+    val outs = Vec((new Coord).asOutput, 4)
+  }
+  val coords = Wire(Vec(new Coord, 4))
+  for (i <- 0 until 4) {
+    coords(i)  := io.in
+    io.outs(i) := coords(i)
+  }
+}
+
+class BundleWireTester(c: BundleWire) extends Tester(c) {
+  for (t <- 0 until 4) {
+    val test_in_x = rnd.nextInt(256)
+    val test_in_y = rnd.nextInt(256)
+    poke(c.io.in.x, test_in_x)
+    poke(c.io.in.y, test_in_y)
+    step(1)
+    for (i <- 0 until 4) {
+      expect(c.io.outs(i).x, test_in_x)
+      expect(c.io.outs(i).y, test_in_y)
+    }
+  }
+}
+
diff --git a/src/test/scala/ChiselTests/ComplexAssign.scala b/src/test/scala/ChiselTests/ComplexAssign.scala
new file mode 100644
index 00000000..ee0cd0d3
--- /dev/null
+++ b/src/test/scala/ChiselTests/ComplexAssign.scala
@@ -0,0 +1,40 @@
+package ChiselTests
+import Chisel._
+
+class Complex[T <: Data](val re: T, val im: T, dir: Direction = OUTPUT)
+    extends Bundle(dir) {
+  override def cloneType: this.type = 
+    new Complex(re.cloneType, im.cloneType, dir).asInstanceOf[this.type]
+}
+
+class ComplexAssign(W: Int) extends Module {
+  val io = new Bundle {
+    val e   = new Bool(INPUT)
+    val in  = new Complex(Bits(width = W), Bits(width = W), INPUT)
+    val out = new Complex(Bits(width = W), Bits(width = W), OUTPUT)
+  }
+  when (io.e) {
+    val w = Wire(new Complex(Bits(width = W), Bits(width = W)))
+    w := io.in
+    io.out.re := w.re
+    io.out.im := w.im
+  } .otherwise {
+    io.out.re := Bits(0)
+    io.out.im := Bits(0)
+  }
+}
+
+class ComplexAssignTester(c: ComplexAssign) extends Tester(c) {
+  for (t <- 0 until 4) {
+    val test_e     = rnd.nextInt(2)
+    val test_in_re = rnd.nextInt(256)
+    val test_in_im = rnd.nextInt(256)
+
+    poke(c.io.e,     test_e)
+    poke(c.io.in.re, test_in_re)
+    poke(c.io.in.im, test_in_im)
+    step(1)
+    expect(c.io.out.re, if (test_e == 1) test_in_re else 0)
+    expect(c.io.out.im, if (test_e == 1) test_in_im else 0)
+  }
+}
diff --git a/src/test/scala/ChiselTests/Counter.scala b/src/test/scala/ChiselTests/Counter.scala
new file mode 100644
index 00000000..cab61c53
--- /dev/null
+++ b/src/test/scala/ChiselTests/Counter.scala
@@ -0,0 +1,44 @@
+package ChiselTests
+import Chisel._
+
+object Counter {
+  def wrapAround(n: UInt, max: UInt) = 
+    Mux(n > max, UInt(0), n)
+  def apply(max: UInt, en: Bool, amt: UInt): UInt = {
+    val x = Reg(init=UInt(0, max.getWidth))
+    when (en) { x := wrapAround(x +% amt, max) }
+    x
+  }
+}
+
+class Counter extends Module {
+  val io = new Bundle {
+    val inc = Bool(INPUT)
+    val amt = UInt(INPUT,  4)
+    val tot = UInt(OUTPUT, 8)
+  }
+  io.tot := Counter(UInt(255), io.inc, io.amt)
+}
+
+class CounterTester(c: Counter) extends Tester(c) {
+  val maxInt  = 16
+  var curCnt  = 0
+
+  def intWrapAround(n: Int, max: Int) = 
+    if(n > max) 0 else n
+
+  // let it spin for a bit
+  for (i <- 0 until 5) {
+    step(1)
+  }
+
+  for (i <- 0 until 10) {
+    val inc = rnd.nextBoolean()
+    val amt = rnd.nextInt(maxInt)
+    poke(c.io.inc, if (inc) 1 else 0)
+    poke(c.io.amt, amt)
+    step(1)
+    curCnt = if(inc) intWrapAround(curCnt + amt, 255) else curCnt
+    expect(c.io.tot, curCnt)
+  }
+}
diff --git a/src/test/scala/ChiselTests/Decoder.scala b/src/test/scala/ChiselTests/Decoder.scala
new file mode 100644
index 00000000..c9b9f418
--- /dev/null
+++ b/src/test/scala/ChiselTests/Decoder.scala
@@ -0,0 +1,20 @@
+package ChiselTests
+import Chisel._
+
+object Insts {
+  def ADD = MInt("b0000000??????????000?????0110011")
+}
+
+class Decoder extends Module {
+  val io = new Bundle {
+    val inst  = UInt(INPUT, 32)
+    val isAdd = Bool(OUTPUT)
+  }
+  io.isAdd := (Insts.ADD === io.inst)
+}
+
+class DecoderTester(c: Decoder) extends Tester(c) {
+  poke(c.io.inst, 0x1348533)
+  step(1)
+  expect(c.io.isAdd, int(true))
+}
diff --git a/src/test/scala/ChiselTests/DirChange.scala b/src/test/scala/ChiselTests/DirChange.scala
new file mode 100644
index 00000000..882d4844
--- /dev/null
+++ b/src/test/scala/ChiselTests/DirChange.scala
@@ -0,0 +1,17 @@
+package ChiselTests
+import Chisel._
+
+class DirChange extends Module {
+  val io = new Bundle {
+    val test1 = UInt(INPUT, 5).asOutput
+    val test2 = UInt(OUTPUT, 5).asInput
+    val test3 = Vec( UInt(OUTPUT, 2), 10)
+    val test4 = new Bundle {
+      val test41 = SInt(INPUT, 5)
+      val test42 = SInt(OUTPUT, 5)
+    }.asInput
+  }.flip
+}
+
+class DirChangeTester(c: DirChange) extends Tester(c) {
+}
diff --git a/src/test/scala/ChiselTests/EnableShiftRegister.scala b/src/test/scala/ChiselTests/EnableShiftRegister.scala
new file mode 100644
index 00000000..49825271
--- /dev/null
+++ b/src/test/scala/ChiselTests/EnableShiftRegister.scala
@@ -0,0 +1,39 @@
+package ChiselTests
+import Chisel._
+
+class EnableShiftRegister extends Module {
+  val io = new Bundle {
+    val in    = UInt(INPUT, 4)
+    val shift = Bool(INPUT)
+    val out   = UInt(OUTPUT, 4)
+  }
+  val r0 = Reg(init = UInt(0, 4))
+  val r1 = Reg(init = UInt(0, 4))
+  val r2 = Reg(init = UInt(0, 4))
+  val r3 = Reg(init = UInt(0, 4))
+  when(io.shift) {
+    r0 := io.in
+    r1 := r0
+    r2 := r1
+    r3 := r2
+  }
+  io.out := r3
+}
+
+class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
+  val reg = Array.fill(4){ 0 }
+  for (t <- 0 until 16) {
+    val in    = rnd.nextInt(16)
+    val shift = rnd.nextInt(2)
+    println("SHIFT " + shift + " IN " + in)
+    poke(c.io.in,    in)
+    poke(c.io.shift, shift)
+    step(1)
+    if (shift == 1) {
+      for (i <- 3 to 1 by -1)
+        reg(i) = reg(i-1)
+      reg(0) = in
+    }
+    expect(c.io.out, reg(3))
+  }
+}
diff --git a/src/test/scala/ChiselTests/GCD.scala b/src/test/scala/ChiselTests/GCD.scala
new file mode 100644
index 00000000..2702aaec
--- /dev/null
+++ b/src/test/scala/ChiselTests/GCD.scala
@@ -0,0 +1,31 @@
+package ChiselTests
+import Chisel._
+
+class GCD extends Module {
+  val io = new Bundle {
+    val a  = Bits(INPUT,  16)
+    val b  = Bits(INPUT,  16)
+    val e  = Bool(INPUT)
+    val z  = Bits(OUTPUT, 16)
+    val v  = Bool(OUTPUT)
+  }
+  val x = Reg(Bits(width = 16))
+  val y = Reg(Bits(width = 16))
+  when (x > y)   { x := x -% y }
+  .otherwise     { y := y -% x }
+  when (io.e) { x := io.a; y := io.b }
+  io.z := x
+  io.v := y === Bits(0)
+}
+
+class GCDTester(c: GCD) extends Tester(c) {
+  val (a, b, z) = (64, 48, 16)
+  do {
+    val first = if (t == 0) 1 else 0;
+    poke(c.io.a, a)
+    poke(c.io.b, b)
+    poke(c.io.e, first)
+    step(1)
+  } while (t <= 1 || peek(c.io.v) == 0)
+  expect(c.io.z, z)
+}
diff --git a/src/test/scala/ChiselTests/LFSR16.scala b/src/test/scala/ChiselTests/LFSR16.scala
new file mode 100644
index 00000000..2683247f
--- /dev/null
+++ b/src/test/scala/ChiselTests/LFSR16.scala
@@ -0,0 +1,30 @@
+package ChiselTests
+import Chisel._
+
+class LFSR16 extends Module {
+  val io = new Bundle {
+    val inc = Bool(INPUT)
+    val out = UInt(OUTPUT, 16)
+  }
+  val res = Reg(init = UInt(1, 16))
+  when (io.inc) { 
+    val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) 
+    res := nxt_res
+  }
+  io.out := res
+}
+
+
+class LFSR16Tester(c: LFSR16) extends Tester(c) {
+  var res = 1
+  for (t <- 0 until 16) {
+    val inc = rnd.nextInt(2)
+    poke(c.io.inc, inc)
+    step(1)
+    if (inc == 1) {
+      val bit = ((res >> 0) ^ (res >> 2) ^ (res >> 3) ^ (res >> 5) ) & 1;
+      res = (res >> 1) | (bit << 15);
+    }
+    expect(c.io.out, res)
+  }
+}
diff --git a/src/test/scala/ChiselTests/MemorySearch.scala b/src/test/scala/ChiselTests/MemorySearch.scala
new file mode 100644
index 00000000..e58005c2
--- /dev/null
+++ b/src/test/scala/ChiselTests/MemorySearch.scala
@@ -0,0 +1,43 @@
+package ChiselTests
+import Chisel._
+
+class MemorySearch extends Module {
+  val io = new Bundle {
+    val target  = UInt(INPUT,  4)
+    val en      = Bool(INPUT)
+    val done    = Bool(OUTPUT)
+    val address = UInt(OUTPUT, 3)
+  }
+  val vals  = Array(0, 4, 15, 14, 2, 5, 13)
+  val index = Reg(init = UInt(0, width = 3))
+  val elts  = Vec(vals.map(UInt(_,4)))
+  // val elts  = Mem(UInt(width = 32), 8)
+  val elt  = elts(index)
+  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
+  when (io.en) {
+    index := UInt(0)
+  } .elsewhen (!end) {
+    index := index +% UInt(1)
+  }
+  io.done    := end
+  io.address := index
+}
+
+class MemorySearchTester(c: MemorySearch) extends Tester(c) {
+  val list = c.vals
+  val n = 8
+  val maxT = n * (list.length + 3)
+  for (k <- 0 until n) {
+    val target = rnd.nextInt(16)
+    poke(c.io.en,     1)
+    poke(c.io.target, target)
+    step(1)
+    poke(c.io.en,     0)
+    do {
+      step(1)
+    } while (peek(c.io.done) == 0 && t < maxT)
+    val addr = peek(c.io.address).toInt
+    expect(addr == list.length || list(addr) == target, 
+           "LOOKING FOR " + target + " FOUND " + addr)
+  }
+}
diff --git a/src/test/scala/ChiselTests/ModuleVec.scala b/src/test/scala/ChiselTests/ModuleVec.scala
new file mode 100644
index 00000000..9d76760d
--- /dev/null
+++ b/src/test/scala/ChiselTests/ModuleVec.scala
@@ -0,0 +1,34 @@
+package ChiselTests
+import Chisel._
+
+class PlusOne extends Module {
+  val io = new Bundle {
+    val in  = UInt(INPUT,  32)
+    val out = UInt(OUTPUT, 32)
+  }
+  io.out := io.in + UInt(1)
+}
+
+class ModuleVec(val n: Int) extends Module {
+  val io = new Bundle {
+    val ins  = Vec(UInt(INPUT,  32), n)
+    val outs = Vec(UInt(OUTPUT, 32), n)
+  }
+  val pluses = Vec.fill(n){ Module(new PlusOne).io }
+  for (i <- 0 until n) {
+    pluses(i).in := io.ins(i)
+    io.outs(i)   := pluses(i).out 
+  }
+}
+
+
+class ModuleVecTester(c: ModuleVec) extends Tester(c) {
+  for (t <- 0 until 16) {
+    val test_ins = Array.fill(c.n){ rnd.nextInt(256) }
+    for (i <- 0 until c.n) 
+      poke(c.io.ins(i), test_ins(i))
+    step(1)
+    for (i <- 0 until c.n) 
+      expect(c.io.outs(i), test_ins(i) + 1)
+  }
+}
diff --git a/src/test/scala/ChiselTests/ModuleWire.scala b/src/test/scala/ChiselTests/ModuleWire.scala
new file mode 100644
index 00000000..13e74a06
--- /dev/null
+++ b/src/test/scala/ChiselTests/ModuleWire.scala
@@ -0,0 +1,30 @@
+package ChiselTests
+import Chisel._
+
+class Inc extends Module {
+  val io = new Bundle {
+    val in  = UInt(INPUT,  32)
+    val out = UInt(OUTPUT, 32)
+  }
+  io.out := io.in + UInt(1)
+}
+
+class ModuleWire extends Module {
+  val io = new Bundle {
+    val in  = UInt(INPUT,  32)
+    val out = UInt(OUTPUT, 32)
+  }
+  val inc = Module(new Inc).io 
+  inc.in := io.in
+  io.out := inc.out 
+}
+
+
+class ModuleWireTester(c: ModuleWire) extends Tester(c) {
+  for (t <- 0 until 16) {
+    val test_in = rnd.nextInt(256)
+    poke(c.io.in, test_in)
+    step(1)
+    expect(c.io.out, test_in + 1)
+  }
+}
diff --git a/src/test/scala/ChiselTests/Mul.scala b/src/test/scala/ChiselTests/Mul.scala
new file mode 100644
index 00000000..9f7c604c
--- /dev/null
+++ b/src/test/scala/ChiselTests/Mul.scala
@@ -0,0 +1,34 @@
+package ChiselTests
+import Chisel._
+import scala.collection.mutable.ArrayBuffer
+
+class Mul(val w: Int) extends Module {
+  val io = new Bundle {
+    val x   = UInt(INPUT,  w)
+    val y   = UInt(INPUT,  w)
+    val z   = UInt(OUTPUT, 2 * w)
+  }
+  val muls = new ArrayBuffer[UInt]()
+
+  val n = 1 << w
+
+  for (i <- 0 until n)
+    for (j <- 0 until n)
+      muls += UInt(i * j, 2 * w)
+  val tbl = Vec(muls)
+  // val ad = (io.x << w) | io.y
+  io.z := tbl(((io.x << w) | io.y).toUInt)
+}
+
+
+class MulTester(c: Mul) extends Tester(c) {
+  val maxInt  = 1 << c.w
+  for (i <- 0 until 10) {
+    val x = rnd.nextInt(maxInt)
+    val y = rnd.nextInt(maxInt)
+    poke(c.io.x, x)
+    poke(c.io.y, y)
+    step(1)
+    expect(c.io.z, (x * y))
+  }
+}
diff --git a/src/test/scala/ChiselTests/Outer.scala b/src/test/scala/ChiselTests/Outer.scala
new file mode 100644
index 00000000..8e206f90
--- /dev/null
+++ b/src/test/scala/ChiselTests/Outer.scala
@@ -0,0 +1,32 @@
+package ChiselTests
+import Chisel._
+
+class Inner extends Module {
+  val io = new Bundle {
+    val in  = Bits(INPUT, 8)
+    val out = Bits(OUTPUT, 8)
+  }
+  io.out := io.in +% Bits(1)
+}
+
+class Outer extends Module {
+  val io = new Bundle { 
+    val in  = Bits(INPUT, 8)
+    val out = Bits(OUTPUT, 8)
+  }
+  // val c = Module(new Inner)
+  val c = Array(Module(new Inner))
+  // val w = Wire(Bits(NO_DIR, 8))
+  // w := io.in
+  c(0).io.in := io.in
+  io.out  := (c(0).io.out * Bits(2))(7,0)
+}
+
+class OuterTester(c: Outer) extends Tester(c) {
+  for (t <- 0 until 16) {
+    val test_in = rnd.nextInt(256)
+    poke(c.io.in, test_in)
+    step(1)
+    expect(c.io.out, ((test_in + 1) * 2)&255)
+  }
+}
diff --git a/src/test/scala/ChiselTests/Pads.scala b/src/test/scala/ChiselTests/Pads.scala
new file mode 100644
index 00000000..a5c03d0b
--- /dev/null
+++ b/src/test/scala/ChiselTests/Pads.scala
@@ -0,0 +1,28 @@
+package ChiselTests
+import Chisel._
+
+class Pads extends Module {
+  val io = new Bundle {
+    val a   = Bits(INPUT,  4)
+    val asp = Bits(OUTPUT, 8)
+    val aup = Bits(OUTPUT, 8)
+  }
+  io.asp := io.a.toSInt
+  io.aup := io.a.toUInt
+}
+
+class PadsTester(c: Pads) extends Tester(c) {
+  def pads(x: BigInt, s: Int, w: Int) = {
+    val sign  = (x & (1 << (s-1)))
+    val wmask = (1 << w) - 1
+    val bmask = (1 << s) - 1
+    if (sign == 0) x else ((~bmask | x) & wmask)
+  }
+  for (t <- 0 until 16) {
+    val test_a = rnd.nextInt(1 << 4)
+    poke(c.io.a, test_a)
+    step(1)
+    expect(c.io.asp, pads(test_a, 4, 8))
+    expect(c.io.aup, test_a)
+  }
+}
diff --git a/src/test/scala/ChiselTests/RegisterVecShift.scala b/src/test/scala/ChiselTests/RegisterVecShift.scala
new file mode 100644
index 00000000..2f89ead7
--- /dev/null
+++ b/src/test/scala/ChiselTests/RegisterVecShift.scala
@@ -0,0 +1,55 @@
+package ChiselTests
+import Chisel._
+
+class RegisterVecShift extends Module {
+  val io = new Bundle {
+    val ins   = Vec(UInt(INPUT, 4), 4)
+    // val ins   = Vec.fill(4){ UInt(INPUT, 4) }
+    val load  = Bool(INPUT)
+    val shift = Bool(INPUT)
+    val out   = UInt(OUTPUT, 4)
+  }
+  // val delays = Reg( init = Vec.fill(4){ UInt(0, 4) } )
+  val delays = Reg( Vec(UInt(width = 4), 4) )
+  when (reset) {
+    delays := Vec.fill(4){ UInt(0, 4) }
+  }
+  when (io.load) {
+    delays(0) := io.ins(0)
+    delays(1) := io.ins(1)
+    delays(2) := io.ins(2)
+    delays(3) := io.ins(3)
+  } .elsewhen(io.shift) {
+    delays(0) := io.ins(0)
+    delays(1) := delays(0)
+    delays(2) := delays(1)
+    delays(3) := delays(2)
+  }
+  io.out := delays(3)
+}
+
+
+class RegisterVecShiftTester(c: RegisterVecShift) extends Tester(c) {
+  val reg = Array.fill(4){ 0 }
+  val ins = Array.fill(4){ 0 }
+  for (t <- 0 until 16) {
+    for (i <- 0 until 4)
+      ins(i) = rnd.nextInt(16)
+    val shift = rnd.nextInt(2)
+    val load  = rnd.nextInt(2)
+    for (i <- 0 until 4)
+      poke(c.io.ins(i), ins(i))
+    poke(c.io.load,  load)
+    poke(c.io.shift, shift)
+    step(1)
+    if (load == 1) {
+      for (i <- 0 until 4) 
+        reg(i) = ins(i)
+    } else if (shift == 1) {
+      for (i <- 3 to 1 by -1)
+        reg(i) = reg(i-1)
+      reg(0) = ins(0)
+    }
+    expect(c.io.out, reg(3))
+  }
+}
diff --git a/src/test/scala/ChiselTests/Risc.scala b/src/test/scala/ChiselTests/Risc.scala
new file mode 100644
index 00000000..ec5f1d94
--- /dev/null
+++ b/src/test/scala/ChiselTests/Risc.scala
@@ -0,0 +1,106 @@
+package ChiselTests
+import Chisel._
+
+class Risc extends Module {
+  val io = new Bundle {
+    val isWr   = Bool(INPUT)
+    val wrAddr = UInt(INPUT, 8)
+    val wrData = Bits(INPUT, 32)
+    val boot   = Bool(INPUT)
+    val valid  = Bool(OUTPUT)
+    val out    = Bits(OUTPUT, 32)
+  }
+  val file = Mem(Bits(width = 32), 256)
+  val code = Mem(Bits(width = 32), 256)
+  val pc   = Reg(init=UInt(0, 8))
+  
+  val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2)
+
+  val inst = code(pc)
+  val op   = inst(31,24)
+  val rci  = inst(23,16)
+  val rai  = inst(15, 8)
+  val rbi  = inst( 7, 0)
+
+  val ra = Mux(rai === Bits(0), Bits(0), file(rai))
+  val rb = Mux(rbi === Bits(0), Bits(0), file(rbi))
+  val rc = Wire(Bits(width = 32))
+
+  io.valid := Bool(false)
+  io.out   := Bits(0)
+  rc       := Bits(0)
+
+  when (io.isWr) {
+    code(io.wrAddr) := io.wrData
+  } .elsewhen (io.boot) {
+    pc := UInt(0)
+  } .otherwise {
+    switch(op) {
+      is(add_op) { rc := ra +% rb }
+      is(imm_op) { rc := (rai << 8) | rbi }
+    }
+    io.out := rc
+    when (rci === UInt(255)) {
+      io.valid := Bool(true)
+    } .otherwise {
+      file(rci) := rc
+    }
+    pc := pc +% UInt(1)
+  }
+}
+
+class RiscTester(c: Risc) extends Tester(c) {
+  def wr(addr: BigInt, data: BigInt)  = {
+    poke(c.io.isWr,   1)
+    poke(c.io.wrAddr, addr)
+    poke(c.io.wrData, data)
+    step(1)
+  }
+  def boot()  = {
+    poke(c.io.isWr, 0)
+    poke(c.io.boot, 1)
+    step(1)
+  }
+  def tick(isBoot: Boolean)  = {
+    if (isBoot)
+      poke(c.io.boot, 0)
+    step(1)
+  }
+  def I (op: UInt, rc: Int, ra: Int, rb: Int) = {
+    // val cr = Cat(op, UInt(rc, 8), UInt(ra, 8), UInt(rb, 8)).litValue()
+    val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb
+    println("I = " + cr)
+    cr
+  }
+
+  val app  = Array(I(c.imm_op,   1, 0, 1), // r1 <- 1
+                   I(c.add_op,   1, 1, 1), // r1 <- r1 + r1
+                   I(c.add_op,   1, 1, 1), // r1 <- r1 + r1
+                   I(c.add_op, 255, 1, 0)) // rh <- r1
+  wr(0, 0) // skip reset
+  for (addr <- 0 until app.length) 
+    wr(addr, app(addr))
+  def dump(k: Int) {
+    println("K = " + k)
+    peek(c.ra)
+    peek(c.rb)
+    peek(c.rc)
+    peek(c.io.out)
+    peek(c.pc)
+    peek(c.inst)
+    peek(c.op)
+    peek(c.rci)
+    peek(c.rai)
+    peek(c.rbi)
+    peekAt(c.file, 1)
+  }
+  boot()
+  dump(0)
+  var k = 0
+  do {
+    tick(k == 0); k += 1
+    dump(k)
+  } while (!(peek(c.io.valid) == 1 || k > 10))
+  expect(k <= 10, "TIME LIMIT")
+  expect(c.io.out, 4)
+}
diff --git a/src/test/scala/ChiselTests/Rom.scala b/src/test/scala/ChiselTests/Rom.scala
new file mode 100644
index 00000000..7c7eb1ac
--- /dev/null
+++ b/src/test/scala/ChiselTests/Rom.scala
@@ -0,0 +1,23 @@
+package ChiselTests
+import Chisel._
+
+class Rom extends Module {
+  val io = new Bundle {
+    val addr = UInt(INPUT,  4)
+    val out  = UInt(OUTPUT, 5)
+  }
+  val r = Vec(Range(0, 1 << 4).map(i => UInt(i * 2, width = 5)))
+  io.out := r(io.addr)
+}
+
+
+class RomTester(c: Rom) extends Tester(c) {
+  val r = Array.tabulate(1 << 4){ i => i * 2}
+  for (i <- 0 until 10) {
+    val a = rnd.nextInt(1 << 4)
+    poke(c.io.addr, a)
+    step(1)
+    expect(c.io.out, r(a))
+  }
+
+}
diff --git a/src/test/scala/ChiselTests/SIntOps.scala b/src/test/scala/ChiselTests/SIntOps.scala
new file mode 100644
index 00000000..5fd02c37
--- /dev/null
+++ b/src/test/scala/ChiselTests/SIntOps.scala
@@ -0,0 +1,81 @@
+package ChiselTests
+import Chisel._
+
+class SIntOps extends Module {
+  val io = new Bundle {
+    val a = SInt(INPUT, 16)
+    val b = SInt(INPUT, 16)
+    val addout = SInt(OUTPUT, 16)
+    val subout = SInt(OUTPUT, 16)
+    val timesout = SInt(OUTPUT, 16)
+    val divout = SInt(OUTPUT, 16)
+    val modout = SInt(OUTPUT, 16)
+    val lshiftout = SInt(OUTPUT, 16)
+    val rshiftout = SInt(OUTPUT, 16)
+    val lessout = Bool(OUTPUT)
+    val greatout = Bool(OUTPUT)
+    val eqout = Bool(OUTPUT)
+    val noteqout = Bool(OUTPUT)
+    val lesseqout = Bool(OUTPUT)
+    val greateqout = Bool(OUTPUT)
+    val negout = SInt(OUTPUT, 16)
+  }
+
+  val a = io.a
+  val b = io.b
+  val ub = b.toUInt
+
+  io.addout := a +% b
+  io.subout := a -% b
+  io.timesout := (a * b)(15, 0)
+  // TODO: 
+  // io.divout := a / Mux(b === SInt(0), SInt(1), b)
+  io.divout := (a * b)(15, 0)
+  // io.divout := (a / b)(15, 0)
+  io.modout := UInt(0)
+  io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
+  io.rshiftout := (a >> 8) // (a >> ub).toSInt
+  io.lessout := a < b
+  io.greatout := a > b
+  io.eqout := a === b
+  io.noteqout := (a != b)
+  io.lesseqout := a <= b
+  io.greateqout := a >= b
+  // io.negout := -a(15, 0).toSInt
+  io.negout := (SInt(0) -% a)
+}
+
+class SIntOpsTester(c: SIntOps) extends Tester(c) {
+  def sintExpect(d: Bits, x: BigInt) {
+    val mask = (1 << 16) - 1
+    val sbit = (1 << 15)
+    val y = x & mask
+    val r = if ((y & sbit) == 0) y else (-(~y)-1)
+    expect(d, r)
+  }
+  for (t <- 0 until 16) {
+    val test_a = (1 << 15) - rnd.nextInt(1 << 16)
+    val test_b = (1 << 15) - rnd.nextInt(1 << 16)
+    poke(c.io.a, test_a)
+    poke(c.io.b, test_b)
+    step(1)
+    sintExpect(c.io.addout, test_a + test_b)
+    sintExpect(c.io.subout, test_a - test_b)
+    sintExpect(c.io.timesout, test_a * test_b)
+    // sintExpect(c.io.divout, if (test_b == 0) 0 else test_a / test_b)
+    sintExpect(c.io.divout, test_a * test_b)
+    // sintExpect(c.io.modout, test_a % test_b)
+    // sintExpect(c.io.lshiftout, test_a << (test_b&15))
+    // sintExpect(c.io.rshiftout, test_a >> test_b)
+    sintExpect(c.io.lshiftout, test_a << 12)
+    sintExpect(c.io.rshiftout, test_a >> 8)
+    sintExpect(c.io.negout, -test_a)
+    expect(c.io.lessout, int(test_a < test_b))
+    expect(c.io.greatout, int(test_a > test_b))
+    expect(c.io.eqout, int(test_a == test_b))
+    expect(c.io.noteqout, int(test_a != test_b))
+    expect(c.io.lessout, int(test_a <= test_b))
+    expect(c.io.greateqout, int(test_a >= test_b))
+  }
+}
+
diff --git a/src/test/scala/ChiselTests/Stack.scala b/src/test/scala/ChiselTests/Stack.scala
new file mode 100644
index 00000000..afcbc8bc
--- /dev/null
+++ b/src/test/scala/ChiselTests/Stack.scala
@@ -0,0 +1,62 @@
+package ChiselTests
+import scala.collection.mutable.{Stack => ScalaStack}
+import Chisel._
+
+class Stack(val depth: Int) extends Module {
+  val io = new Bundle {
+    val push    = Bool(INPUT)
+    val pop     = Bool(INPUT)
+    val en      = Bool(INPUT)
+    val dataIn  = UInt(INPUT,  32)
+    val dataOut = UInt(OUTPUT, 32)
+  }
+
+  val stack_mem = Mem(UInt(width = 32), depth)
+  val sp        = Reg(init = UInt(0, width = log2Up(depth+1)))
+  val out       = Reg(init = UInt(0, width = 32))
+
+  when (io.en) {
+    when(io.push && (sp < UInt(depth))) {
+      stack_mem(sp) := io.dataIn
+      sp := sp +% UInt(1)
+    } .elsewhen(io.pop && (sp > UInt(0))) {
+      sp := sp -% UInt(1)
+    }
+    when (sp > UInt(0)) {
+      out := stack_mem(sp -% UInt(1))
+    }
+  }
+  io.dataOut := out
+}
+
+class StackTester(c: Stack) extends Tester(c) {
+  var nxtDataOut = 0
+  var dataOut = 0
+  val stack = new ScalaStack[Int]()
+
+  for (t <- 0 until 16) {
+    val enable  = rnd.nextInt(2)
+    val push    = rnd.nextInt(2)
+    val pop     = rnd.nextInt(2)
+    val dataIn  = rnd.nextInt(256)
+
+    if (enable == 1) {
+      dataOut = nxtDataOut
+      if (push == 1 && stack.length < c.depth) {
+        stack.push(dataIn)
+      } else if (pop == 1 && stack.length > 0) {
+        stack.pop()
+      }
+      if (stack.length > 0) {
+        nxtDataOut = stack.top
+      }
+    }
+
+    poke(c.io.pop,    pop)
+    poke(c.io.push,   push)
+    poke(c.io.en,     enable)
+    poke(c.io.dataIn, dataIn)
+    step(1)
+    expect(c.io.dataOut, dataOut)
+  }
+}
diff --git a/src/test/scala/ChiselTests/Tbl.scala b/src/test/scala/ChiselTests/Tbl.scala
new file mode 100644
index 00000000..390f5882
--- /dev/null
+++ b/src/test/scala/ChiselTests/Tbl.scala
@@ -0,0 +1,31 @@
+package ChiselTests
+import Chisel._
+
+class Tbl extends Module {
+  val io = new Bundle {
+    val  i  = Bits(INPUT,  16)
+    val we  = Bool(INPUT)
+    val  d  = Bits(INPUT,  16)
+    val  o  = Bits(OUTPUT, 16)
+  }
+  val m = Mem(Bits(width = 10), 256)
+  io.o := Bits(0)
+  when (io.we) { m(io.i) := io.d(9, 0) }
+  .otherwise   { io.o := m(io.i) }
+}
+
+class TblTester(c: Tbl) extends Tester(c) {
+  val m = Array.fill(1 << 16){ 0 }
+  for (t <- 0 until 16) {
+    val i  = rnd.nextInt(1 << 16)
+    val d  = rnd.nextInt(1 << 16)
+    val we = rnd.nextInt(2)
+    poke(c.io.i,   i)
+    poke(c.io.we, we)
+    poke(c.io.d,   d)
+    step(1)
+    expect(c.io.o, if (we == 1) 0 else m(i))
+    if (we == 1)
+      m(i) = d
+  }
+}
diff --git a/src/test/scala/ChiselTests/UIntOps.scala b/src/test/scala/ChiselTests/UIntOps.scala
new file mode 100644
index 00000000..41116029
--- /dev/null
+++ b/src/test/scala/ChiselTests/UIntOps.scala
@@ -0,0 +1,71 @@
+package ChiselTests
+import Chisel._
+
+class UIntOps extends Module {
+  val io = new Bundle {
+    val a = UInt(INPUT, 16)
+    val b = UInt(INPUT, 16)
+    val addout = UInt(OUTPUT, 16)
+    val subout = UInt(OUTPUT, 16)
+    val timesout = UInt(OUTPUT, 16)
+    val divout = UInt(OUTPUT, 16)
+    val modout = UInt(OUTPUT, 16)
+    val lshiftout = UInt(OUTPUT, 16)
+    val rshiftout = UInt(OUTPUT, 16)
+    val lessout = Bool(OUTPUT)
+    val greatout = Bool(OUTPUT)
+    val eqout = Bool(OUTPUT)
+    val noteqout = Bool(OUTPUT)
+    val lesseqout = Bool(OUTPUT)
+    val greateqout = Bool(OUTPUT)
+  }
+
+  val a = io.a
+  val b = io.b
+
+  io.addout := a +% b
+  io.subout := a -% b
+  io.timesout := (a * b)(15, 0)
+  io.divout := a / Mux(b === UInt(0), UInt(1), b)
+  // io.modout := a % b
+  // TODO: 
+  io.modout := UInt(0)
+  io.lshiftout := (a << b(3, 0))(15, 0)
+  io.rshiftout := a >> b
+  io.lessout := a < b
+  io.greatout := a > b
+  io.eqout := a === b
+  io.noteqout := (a != b)
+  io.lesseqout := a <= b
+  io.greateqout := a >= b
+}
+
+class UIntOpsTester(c: UIntOps) extends Tester(c) {
+  def uintExpect(d: Bits, x: BigInt) {
+    val mask = (1 << 16) - 1
+    println(" E = " + x + " X&M = " + (x & mask))
+    expect(d, x & mask)
+  }
+  for (t <- 0 until 16) {
+    val test_a = rnd.nextInt(1 << 16)
+    val test_b = rnd.nextInt(1 << 16)
+    println("A = " + test_a + " B = " + test_b)
+    poke(c.io.a, test_a)
+    poke(c.io.b, test_b)
+    step(1)
+    uintExpect(c.io.addout, test_a + test_b)
+    uintExpect(c.io.subout, test_a - test_b)
+    uintExpect(c.io.divout, if (test_b == 0) 0 else test_a / test_b)
+    uintExpect(c.io.timesout, test_a * test_b)
+    // uintExpect(c.io.modout, test_a % test_b)
+    uintExpect(c.io.lshiftout, test_a << (test_b&15))
+    uintExpect(c.io.rshiftout, test_a >> test_b)
+    expect(c.io.lessout, int(test_a < test_b))
+    expect(c.io.greatout, int(test_a > test_b))
+    expect(c.io.eqout, int(test_a == test_b))
+    expect(c.io.noteqout, int(test_a != test_b))
+    expect(c.io.lessout, int(test_a <= test_b))
+    expect(c.io.greateqout, int(test_a >= test_b))
+  }
+}
+
diff --git a/src/test/scala/ChiselTests/VecApp.scala b/src/test/scala/ChiselTests/VecApp.scala
new file mode 100644
index 00000000..c32752d6
--- /dev/null
+++ b/src/test/scala/ChiselTests/VecApp.scala
@@ -0,0 +1,22 @@
+package ChiselTests
+import Chisel._
+
+class VecApp(n: Int, W: Int) extends Module {
+  val io = new Bundle {
+    val a = UInt(INPUT, n)
+    val i = Vec(Bits(INPUT, W), n)
+    // val o = Vec.fill(n){ Bits(OUTPUT, W) }
+    val d = Bits(OUTPUT, W)
+  }
+  // for (j <- 0 until n)
+  //   io.o(j) := io.i(j)
+  // val w = Wire(Vec.fill(n){ Bits(width = W) })
+  // w := io.i
+  // io.o := w
+  // io.d := w(io.a)
+  io.d := io.i(io.a)
+  // io.o := io.i
+}
+
+class VecAppTester(c: VecApp) extends Tester(c) {
+}
diff --git a/src/test/scala/ChiselTests/VecShiftRegister.scala b/src/test/scala/ChiselTests/VecShiftRegister.scala
new file mode 100644
index 00000000..7a761801
--- /dev/null
+++ b/src/test/scala/ChiselTests/VecShiftRegister.scala
@@ -0,0 +1,28 @@
+package ChiselTests
+import Chisel._
+
+class VecShiftRegister extends Module {
+  val io = new Bundle {
+    val ins   = Vec(UInt(INPUT, 4), 4)
+    val load  = Bool(INPUT)
+    val shift = Bool(INPUT)
+    val out   = UInt(OUTPUT, 4)
+  }
+  val delays = Reg(Vec(UInt(width = 4), 4))
+  when (io.load) {
+    delays(0) := io.ins(0)
+    delays(1) := io.ins(1)
+    delays(2) := io.ins(2)
+    delays(3) := io.ins(3)
+  } .elsewhen(io.shift) {
+    delays(0) := io.ins(0)
+    delays(1) := delays(0)
+    delays(2) := delays(1)
+    delays(3) := delays(2)
+  }
+  io.out := delays(3)
+}
+
+
+class VecShiftRegisterTester(c: VecShiftRegister) extends Tester(c) {
+}
diff --git a/src/test/scala/ChiselTests/VendingMachine.scala b/src/test/scala/ChiselTests/VendingMachine.scala
new file mode 100644
index 00000000..787f7e33
--- /dev/null
+++ b/src/test/scala/ChiselTests/VendingMachine.scala
@@ -0,0 +1,55 @@
+package ChiselTests
+import Chisel._
+
+class VendingMachine extends Module {
+  val io = new Bundle {
+    val nickel = Bool(dir = INPUT)
+    val dime   = Bool(dir = INPUT)
+    val valid  = Bool(dir = OUTPUT) }
+  val c = Lit(5, 3){ UInt() }
+  val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
+  val state = Reg(init = sIdle)
+  when (state === sIdle) {
+    when (io.nickel) { state := s5 }
+    when (io.dime)   { state := s10 }
+  }
+  when (state === s5) {
+    when (io.nickel) { state := s10 }
+    when (io.dime)   { state := s15 }
+  }
+  when (state === s10) {
+    when (io.nickel) { state := s15 }
+    when (io.dime)   { state := sOk }
+  }
+  when (state === s15) {
+    when (io.nickel) { state := sOk }
+    when (io.dime)   { state := sOk }
+  }
+  when (state === sOk) {
+    state := sIdle
+  }
+  io.valid := (state === sOk)
+}
+
+
+class VendingMachineTester(c: VendingMachine) extends Tester(c) {
+  var money = 0
+  var isValid = false
+  for (t <- 0 until 20) {
+    val coin     = rnd.nextInt(3)*5
+    val isNickel = coin == 5
+    val isDime   = coin == 10
+
+    // Advance circuit
+    poke(c.io.nickel, int(isNickel))
+    poke(c.io.dime,   int(isDime))
+    step(1)
+
+    // Advance model
+    money = if (isValid) 0 else (money + coin)
+    isValid = money >= 20
+
+    // Compare
+    expect(c.io.valid, int(isValid))
+  }
+}
diff --git a/src/test/scala/ChiselTests/main.scala b/src/test/scala/ChiselTests/main.scala
new file mode 100644
index 00000000..88ec9218
--- /dev/null
+++ b/src/test/scala/ChiselTests/main.scala
@@ -0,0 +1,40 @@
+package ChiselTests
+import Chisel._
+
+object MiniChisel {
+  def main(gargs: Array[String]): Unit = {
+    if (gargs.length < 1)
+      println("Need an argument")
+    val name   = gargs(0)
+    val margs  = Array("--targetDir", "generated")
+    val args   = margs ++ gargs.slice(1, gargs.length) 
+    name match {
+      case "EnableShiftRegister" => chiselMainTest(args, () => Module(new EnableShiftRegister))(c => new EnableShiftRegisterTester(c))
+      case "MemorySearch" => chiselMainTest(args, () => Module(new MemorySearch))(c => new MemorySearchTester(c))
+      case "VecApp" => chiselMainTest(args, () => Module(new VecApp(4,8)))(c => new VecAppTester(c))
+      case "Counter" => chiselMainTest(args, () => Module(new Counter))(c => new CounterTester(c))
+      case "Tbl" => chiselMainTest(args, () => Module(new Tbl))(c => new TblTester(c))
+      case "LFSR16" => chiselMainTest(args, () => Module(new LFSR16))(c => new LFSR16Tester(c))
+      case "Mul" => chiselMainTest(args, () => Module(new Mul(2)))(c => new MulTester(c))
+      case "Decoder" => chiselMainTest(args, () => Module(new Decoder))(c => new DecoderTester(c))
+      case "VecShiftRegister" => chiselMainTest(args, () => Module(new VecShiftRegister))(c => new VecShiftRegisterTester(c))
+      case "RegisterVecShift" => chiselMainTest(args, () => Module(new RegisterVecShift))(c => new RegisterVecShiftTester(c))
+      case "ModuleVec" => chiselMainTest(args, () => Module(new ModuleVec(2)))(c => new ModuleVecTester(c))
+      case "ModuleWire" => chiselMainTest(args, () => Module(new ModuleWire))(c => new ModuleWireTester(c))
+      case "BundleWire" => chiselMainTest(args, () => Module(new BundleWire))(c => new BundleWireTester(c))
+
+      case "Stack" => chiselMainTest(args, () => Module(new Stack(16)))(c => new StackTester(c))
+      case "GCD" => chiselMainTest(args, () => Module(new GCD))(c => new GCDTester(c))
+      case "Risc" => chiselMainTest(args, () => Module(new Risc))(c => new RiscTester(c))
+      case "Rom" => chiselMainTest(args, () => Module(new Rom))(c => new RomTester(c))
+      case "Outer" => chiselMainTest(args, () => Module(new Outer))(c => new OuterTester(c))
+      case "ComplexAssign" => chiselMainTest(args, () => Module(new ComplexAssign(10)))(c => new ComplexAssignTester(c))
+      case "UIntOps" => chiselMainTest(args, () => Module(new UIntOps))(c => new UIntOpsTester(c))
+      case "SIntOps" => chiselMainTest(args, () => Module(new SIntOps))(c => new SIntOpsTester(c))
+      case "BitsOps" => chiselMainTest(args, () => Module(new BitsOps))(c => new BitsOpsTester(c))
+      case "DirChange" => chiselMainTest(args, () => Module(new DirChange))(c => new DirChangeTester(c))
+      case "VendingMachine" => chiselMainTest(args, () => Module(new VendingMachine))(c => new VendingMachineTester(c))
+      case "Pads" => chiselMainTest(args, () => Module(new Pads))(c => new PadsTester(c))
+    }
+  }
+}