Eliminate some doc warnings

2 files changed, 2 insertions, 2 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index a0713379..11a447d1 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -95,7 +95,7 @@ trait BackendCompilationUtilities {
   /** Generates a Verilator invocation to convert Verilog sources to C++
     * simulation sources.
     *
-    * The Verilator prefix will be V$dutFile, and running this will generate
+    * The Verilator prefix will be V\$dutFile, and running this will generate
     * C++ sources and headers as well as a makefile to compile them.
     *
     * @param dutFile name of the DUT .v without the .v extension
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index c9d57759..2f6effbd 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -230,7 +230,7 @@ extends Module(override_reset=override_reset) {
   * @param enq input (enqueue) interface to the queue, also determines width of queue elements
   * @param entries depth (number of elements) of the queue
   *
-  * @returns output (dequeue) interface from the queue
+  * @return output (dequeue) interface from the queue
   *
   * @example {{{
   * consumer.io.in <> Queue(producer.io.out, 16)