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authorducky2016-11-17 15:23:25 -0800
committerducky2016-11-17 15:23:25 -0800
commit29f84617ea30c7dd30c9616bcdb9a1894b8a0762 (patch)
treebe37e6a9106048a09975141afedcc4938015e561
parent815b1c3cb311b7f4dfb7a2f00e0e2d62795bdc6b (diff)
Eliminate some doc warnings
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Binding.scala7
-rw-r--r--src/main/scala/chisel3/Driver.scala2
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala2
3 files changed, 5 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index 467cb4eb..3dfde7c2 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -140,10 +140,9 @@ object Binding {
}
}
- /** Diagnose a binding error caused by a missing IO() wrapper.
- * @param element the element triggering the binding error.
- * @return true if the element is a member of the module's io but ioDefined is false.
- */
+ // Diagnose a binding error caused by a missing IO() wrapper.
+ // element is the element triggering the binding error.
+ // Returns true if the element is a member of the module's io but ioDefined is false.
def isMissingIOWrapper(element: Element): Boolean = {
element._parent match {
case None => false
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index a0713379..11a447d1 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -95,7 +95,7 @@ trait BackendCompilationUtilities {
/** Generates a Verilator invocation to convert Verilog sources to C++
* simulation sources.
*
- * The Verilator prefix will be V$dutFile, and running this will generate
+ * The Verilator prefix will be V\$dutFile, and running this will generate
* C++ sources and headers as well as a makefile to compile them.
*
* @param dutFile name of the DUT .v without the .v extension
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index c9d57759..2f6effbd 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -230,7 +230,7 @@ extends Module(override_reset=override_reset) {
* @param enq input (enqueue) interface to the queue, also determines width of queue elements
* @param entries depth (number of elements) of the queue
*
- * @returns output (dequeue) interface from the queue
+ * @return output (dequeue) interface from the queue
*
* @example {{{
* consumer.io.in <> Queue(producer.io.out, 16)