diff options
| author | Schuyler Eldridge | 2020-04-23 22:33:14 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-05-06 02:22:48 -0400 |
| commit | 23db44a44b10aaa6f34f75732266178e6c714aba (patch) | |
| tree | 757dd739b916e411d216ca7f0938a354ab419dd1 /src | |
| parent | 33cfe8101950721f5756207504162b566c438ba8 (diff) | |
Expose ChiselStage's PhaseManager, rm extra wraps
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/stage/ChiselStage.scala | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index 0068d86f..e4ff77d0 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -28,11 +28,12 @@ class ChiselStage extends Stage with PreservesAll[Phase] { Dependency[chisel3.stage.phases.Convert], Dependency[chisel3.stage.phases.MaybeFirrtlStage] ) + final lazy val phaseManager = new PhaseManager(targets) { + override val wrappers = Seq( (a: Phase) => DeletedWrapper(a) ) + } + def run(annotations: AnnotationSeq): AnnotationSeq = try { - new PhaseManager(targets) { override val wrappers = Seq( (a: Phase) => DeletedWrapper(a) ) } - .transformOrder - .map(firrtl.options.phases.DeletedWrapper(_)) - .foldLeft(annotations)( (a, f) => f.transform(a) ) + phaseManager.transform(annotations) } catch { case ce: ChiselException => val stackTrace = if (!view[ChiselOptions](annotations).printFullStackTrace) { |