From 23db44a44b10aaa6f34f75732266178e6c714aba Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 23 Apr 2020 22:33:14 -0400 Subject: Expose ChiselStage's PhaseManager, rm extra wraps Signed-off-by: Schuyler Eldridge --- src/main/scala/chisel3/stage/ChiselStage.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index 0068d86f..e4ff77d0 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -28,11 +28,12 @@ class ChiselStage extends Stage with PreservesAll[Phase] { Dependency[chisel3.stage.phases.Convert], Dependency[chisel3.stage.phases.MaybeFirrtlStage] ) + final lazy val phaseManager = new PhaseManager(targets) { + override val wrappers = Seq( (a: Phase) => DeletedWrapper(a) ) + } + def run(annotations: AnnotationSeq): AnnotationSeq = try { - new PhaseManager(targets) { override val wrappers = Seq( (a: Phase) => DeletedWrapper(a) ) } - .transformOrder - .map(firrtl.options.phases.DeletedWrapper(_)) - .foldLeft(annotations)( (a, f) => f.transform(a) ) + phaseManager.transform(annotations) } catch { case ce: ChiselException => val stackTrace = if (!view[ChiselOptions](annotations).printFullStackTrace) { -- cgit v1.2.3