Deprecate auto-application of empty argument lists to parameterless functions (#2124)

* Migrate nullary funcs to parameterless versions
* Make deprecation message and dummy arguments clear and consistent

Co-authored-by: Megan Wachs <megan@sifive.com>

5 files changed, 37 insertions, 31 deletions

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index dde2321d..ffbb7e27 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -33,7 +33,10 @@ package object Chisel {
   implicit class AddDirectionToData[T<:Data](target: T) {
     def asInput: T = Input(target)
     def asOutput: T = Output(target)
-    def flip(): T = Flipped(target)
+    def flip: T = Flipped(target)
+
+    @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+    def flip(dummy: Int*): T = flip
   }
 
   implicit class AddDirMethodToData[T<:Data](target: T) {
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 0e05d114..060a684c 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -37,7 +37,10 @@ object ReadyValidIO {
 
     /** Indicates if IO is both ready and valid
      */
-    def fire(): Bool = target.ready && target.valid
+    def fire: Bool = target.ready && target.valid
+
+    @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+    def fire(dummy: Int = 0): Bool = fire
 
     /** Push dat onto the output bits of this interface to let the consumer know it has happened.
       * @param dat the values to assign to bits.
@@ -222,8 +225,8 @@ class Queue[T <: Data](val gen: T,
   val ptr_match = enq_ptr.value === deq_ptr.value
   val empty = ptr_match && !maybe_full
   val full = ptr_match && maybe_full
-  val do_enq = WireDefault(io.enq.fire())
-  val do_deq = WireDefault(io.deq.fire())
+  val do_enq = WireDefault(io.enq.fire)
+  val do_deq = WireDefault(io.deq.fire)
   val flush = io.flush.getOrElse(false.B) 
 
   // when flush is high, empty the queue
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index f2e238e9..222d0ba7 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -44,7 +44,7 @@ class SIntOps extends Module {
   io.noteqout := (a =/= b)
   io.lesseqout := a <= b
   io.greateqout := a >= b
-  // io.negout := -a(15, 0).toSInt
+  io.negout := -a(15, 0).asSInt
   io.negout := (0.S -% a)
 }
 
diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala
index d7dea571..404c3f66 100644
--- a/src/test/scala/chiselTests/StrongEnum.scala
+++ b/src/test/scala/chiselTests/StrongEnum.scala
@@ -257,8 +257,8 @@ class IsLitTester extends BasicTester {
   for (e <- EnumExample.all) {
     val wire = WireDefault(e)
 
-    assert(e.isLit())
-    assert(!wire.isLit())
+    assert(e.isLit)
+    assert(!wire.isLit)
   }
   stop()
 }
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
index d91cd2f4..74d8c005 100644
--- a/src/test/scala/chiselTests/VecLiteralSpec.scala
+++ b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -142,17 +142,17 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
 
   "lowest of vec literal contains least significant bits and " in {
     val y = Vec(4, UInt(8.W)).Lit(0 -> 0xAB.U(8.W), 1 -> 0xCD.U(8.W), 2 -> 0xEF.U(8.W), 3 -> 0xFF.U(8.W))
-    y.litValue() should be(BigInt("FFEFCDAB", 16))
+    y.litValue should be(BigInt("FFEFCDAB", 16))
   }
 
   "the order lits are specified does not matter" in {
     val y = Vec(4, UInt(8.W)).Lit(3 -> 0xFF.U(8.W), 2 -> 0xEF.U(8.W), 1 -> 0xCD.U(8.W), 0 -> 0xAB.U(8.W))
-    y.litValue() should be(BigInt("FFEFCDAB", 16))
+    y.litValue should be(BigInt("FFEFCDAB", 16))
   }
 
   "regardless of the literals widths, packing should be done based on the width of the Vec's gen" in {
     val z = Vec(4, UInt(8.W)).Lit(0 -> 0x2.U, 1 -> 0x2.U, 2 -> 0x2.U, 3 -> 0x3.U)
-    z.litValue() should be(BigInt("03020202", 16))
+    z.litValue should be(BigInt("03020202", 16))
   }
 
   "packing sparse vec lits should not pack, litOption returns None" in {
@@ -221,7 +221,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
         chisel3.assert(outsideVecLit(2) === 0xBB.U)
         chisel3.assert(outsideVecLit(3) === 0xAA.U)
 
-        chisel3.assert(outsideVecLit.litValue().U === outsideVecLit.asUInt())
+        chisel3.assert(outsideVecLit.litValue.U === outsideVecLit.asUInt())
 
         val insideVecLit = Vec(4, UInt(16.W)).Lit(0 -> 0xDD.U, 1 -> 0xCC.U, 2 -> 0xBB.U, 3 -> 0xAA.U)
         chisel3.assert(insideVecLit(0) === 0xDD.U)
@@ -277,15 +277,15 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
       1 -> Vec(3, UInt(4.W)).Lit(0 -> 4.U, 1 -> 5.U, 2 -> 6.U)
     )
 
-    outerVec.litValue() should be (BigInt("654321", 16))
-    outerVec(0).litValue() should be (BigInt("321", 16))
-    outerVec(1).litValue() should be (BigInt("654", 16))
-    outerVec(0)(0).litValue() should be (BigInt(1))
-    outerVec(0)(1).litValue() should be (BigInt(2))
-    outerVec(0)(2).litValue() should be (BigInt(3))
-    outerVec(1)(0).litValue() should be (BigInt(4))
-    outerVec(1)(1).litValue() should be (BigInt(5))
-    outerVec(1)(2).litValue() should be (BigInt(6))
+    outerVec.litValue should be (BigInt("654321", 16))
+    outerVec(0).litValue should be (BigInt("321", 16))
+    outerVec(1).litValue should be (BigInt("654", 16))
+    outerVec(0)(0).litValue should be (BigInt(1))
+    outerVec(0)(1).litValue should be (BigInt(2))
+    outerVec(0)(2).litValue should be (BigInt(3))
+    outerVec(1)(0).litValue should be (BigInt(4))
+    outerVec(1)(1).litValue should be (BigInt(5))
+    outerVec(1)(2).litValue should be (BigInt(6))
   }
 
   "contained vecs should work" in {
@@ -473,19 +473,19 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
       0 -> (new SubBundle).Lit(_.foo -> 0xab.U, _.bar -> 0xc.U),
       1 -> (new SubBundle).Lit(_.foo -> 0xde.U, _.bar -> 0xf.U)
     )
-    vec.litValue().toString(16) should be("defabc")
+    vec.litValue.toString(16) should be("defabc")
   }
 
   "vec literals can have bundle children assembled incrementally" in {
     val bundle1 = (new SubBundle).Lit(_.foo -> 0xab.U, _.bar -> 0xc.U)
     val bundle2 = (new SubBundle).Lit(_.foo -> 0xde.U, _.bar -> 0xf.U)
 
-    bundle1.litValue().toString(16) should be("abc")
-    bundle2.litValue().toString(16) should be("def")
+    bundle1.litValue.toString(16) should be("abc")
+    bundle2.litValue.toString(16) should be("def")
 
     val vec = Vec(2, new SubBundle).Lit(0 -> bundle1, 1 -> bundle2)
 
-    vec.litValue().toString(16) should be("defabc")
+    vec.litValue.toString(16) should be("defabc")
   }
 
   "bundles can contain vec lits" in {
@@ -495,7 +495,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
       val foo = Vec(3, UInt(4.W))
       val bar = Vec(2, UInt(4.W))
     }).Lit(_.foo -> vec1, _.bar -> vec2)
-    bundle.litValue().toString(16) should be("cbaed")
+    bundle.litValue.toString(16) should be("cbaed")
   }
 
   "bundles can contain vec lits in-line" in {
@@ -506,21 +506,21 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
       _.foo -> Vec(3, UInt(4.W)).Lit(0 -> 0xa.U, 1 -> 0xb.U, 2 -> 0xc.U),
       _.bar -> Vec(2, UInt(4.W)).Lit(0 -> 0xd.U, 1 -> 0xe.U)
     )
-    bundle.litValue().toString(16) should be("cbaed")
+    bundle.litValue.toString(16) should be("cbaed")
   }
 
   "Vec.Lit is a trivial Vec literal factory" in {
     val vec = Vec.Lit(0xa.U, 0xb.U)
-    vec(0).litValue() should be(0xa)
-    vec(1).litValue() should be(0xb)
+    vec(0).litValue should be(0xa)
+    vec(1).litValue should be(0xb)
   }
 
   "Vec.Lit bases it's element width on the widest literal supplied" in {
     val vec = Vec.Lit(0xa.U, 0xbbbb.U)
-    vec(0).litValue() should be(0xa)
-    vec(1).litValue() should be(0xbbbb)
+    vec(0).litValue should be(0xa)
+    vec(1).litValue should be(0xbbbb)
     vec.length should be(2)
     vec.getWidth should be(16 * 2)
-    vec.litValue() should be(BigInt("bbbb000a", 16))
+    vec.litValue should be(BigInt("bbbb000a", 16))
   }
 }