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authorJared Barocsi2021-10-05 12:33:23 -0700
committerGitHub2021-10-05 19:33:23 +0000
commit110705eeace4f9165dc6377e55c86a599f37a465 (patch)
tree4e6ed88311fd1ce08cebc0225868d2d103c6fae7
parentce15ad50a5c175db06c3bba5e3bf46b6c5466c47 (diff)
Deprecate auto-application of empty argument lists to parameterless functions (#2124)
* Migrate nullary funcs to parameterless versions * Make deprecation message and dummy arguments clear and consistent Co-authored-by: Megan Wachs <megan@sifive.com>
-rw-r--r--core/src/main/scala/chisel3/Aggregate.scala2
-rw-r--r--core/src/main/scala/chisel3/Bits.scala115
-rw-r--r--core/src/main/scala/chisel3/Clock.scala8
-rw-r--r--core/src/main/scala/chisel3/Data.scala25
-rw-r--r--core/src/main/scala/chisel3/Mem.scala2
-rw-r--r--core/src/main/scala/chisel3/Module.scala2
-rw-r--r--core/src/main/scala/chisel3/Num.scala5
-rw-r--r--core/src/main/scala/chisel3/Reg.scala4
-rw-r--r--core/src/main/scala/chisel3/SeqUtils.scala2
-rw-r--r--core/src/main/scala/chisel3/StrongEnum.scala8
-rw-r--r--core/src/main/scala/chisel3/When.scala9
-rw-r--r--core/src/main/scala/chisel3/internal/Builder.scala12
-rw-r--r--core/src/main/scala/chisel3/internal/prefix.scala4
-rw-r--r--core/src/main/scala/chisel3/package.scala25
-rw-r--r--macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala14
-rw-r--r--src/main/scala/chisel3/compatibility.scala5
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala9
-rw-r--r--src/test/scala/chiselTests/SIntOps.scala2
-rw-r--r--src/test/scala/chiselTests/StrongEnum.scala4
-rw-r--r--src/test/scala/chiselTests/VecLiteralSpec.scala48
20 files changed, 210 insertions, 95 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala
index 1892f7c2..4cf427ff 100644
--- a/core/src/main/scala/chisel3/Aggregate.scala
+++ b/core/src/main/scala/chisel3/Aggregate.scala
@@ -54,7 +54,7 @@ sealed abstract class Aggregate extends Data {
override def litOption: Option[BigInt] = {
// Shift the accumulated value by our width and add in our component, masked by our width.
def shiftAdd(accumulator: Option[BigInt], elt: Data): Option[BigInt] = {
- (accumulator, elt.litOption()) match {
+ (accumulator, elt.litOption) match {
case (Some(accumulator), Some(eltLit)) =>
val width = elt.width.get
val masked = ((BigInt(1) << width) - 1) & eltLit // also handles the negative case with two's complement
diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala
index 670f6e7a..b7a4a1a7 100644
--- a/core/src/main/scala/chisel3/Bits.scala
+++ b/core/src/main/scala/chisel3/Bits.scala
@@ -25,7 +25,10 @@ private[chisel3] sealed trait ToBoolable extends Element {
*
* @note The width must be known and equal to 1
*/
- final def asBool(): Bool = macro SourceInfoWhiteboxTransform.noArg
+ final def asBool: Bool = macro SourceInfoWhiteboxTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def asBool(dummy: Int*): Bool = macro SourceInfoWhiteboxTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool
@@ -222,7 +225,10 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
* @return this $coll with each bit inverted
* @group Bitwise
*/
- final def unary_~ (): Bits = macro SourceInfoWhiteboxTransform.noArg
+ final def unary_~ : Bits = macro SourceInfoWhiteboxTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_~(dummy: Int*): Bits = macro SourceInfoWhiteboxTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_unary_~ (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits
@@ -304,10 +310,16 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
def do_>> (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bits
/** Returns the contents of this wire as a [[scala.collection.Seq]] of [[Bool]]. */
- final def toBools(): Seq[Bool] = macro SourceInfoTransform.noArg
+ final def toBools: Seq[Bool] = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def toBools(dummy: Int*): Seq[Bool] = macro SourceInfoWhiteboxTransform.noArgDummy
/** Returns the contents of this wire as a [[scala.collection.Seq]] of [[Bool]]. */
- final def asBools(): Seq[Bool] = macro SourceInfoTransform.noArg
+ final def asBools: Seq[Bool] = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def asBools(dummy: Int*): Seq[Bool] = macro SourceInfoWhiteboxTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_asBools(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Seq[Bool] =
@@ -318,7 +330,10 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
* @note The arithmetic value is not preserved if the most-significant bit is set. For example, a [[UInt]] of
* width 3 and value 7 (0b111) would become an [[SInt]] of width 3 and value -1.
*/
- final def asSInt(): SInt = macro SourceInfoTransform.noArg
+ final def asSInt: SInt = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def asSInt(dummy: Int*): SInt = macro SourceInfoWhiteboxTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_asSInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt
@@ -410,7 +425,10 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
* $constantWidth
* @group Arithmetic
*/
- final def unary_- (): UInt = macro SourceInfoTransform.noArg
+ final def unary_- : UInt = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_-(dummy: Int*): UInt = macro SourceInfoTransform.noArgDummy
/** Unary negation (constant width)
*
@@ -418,7 +436,10 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
* $constantWidth
* @group Arithmetic
*/
- final def unary_-% (): UInt = macro SourceInfoTransform.noArg
+ final def unary_-% : UInt = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_%(dummy: Int*): UInt = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_unary_- (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) : UInt = 0.U - this
@@ -522,7 +543,7 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
*/
final def ^ (that: UInt): UInt = macro SourceInfoTransform.thatArg
- // override def abs: UInt = macro SourceInfoTransform.noArg
+ // override def abs: UInt = macro SourceInfoTransform.noArgDummy
def do_abs(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = this
/** @group SourceInfoTransformMacro */
@@ -545,21 +566,30 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
* @return a hardware [[Bool]] resulting from every bit of this $coll or'd together
* @group Bitwise
*/
- final def orR(): Bool = macro SourceInfoTransform.noArg
+ final def orR: Bool = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def orR(dummy: Int*): Bool = macro SourceInfoTransform.noArgDummy
/** And reduction operator
*
* @return a hardware [[Bool]] resulting from every bit of this $coll and'd together
* @group Bitwise
*/
- final def andR(): Bool = macro SourceInfoTransform.noArg
+ final def andR: Bool = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def andR(dummy: Int*): Bool = macro SourceInfoTransform.noArgDummy
/** Exclusive or (xor) reduction operator
*
* @return a hardware [[Bool]] resulting from every bit of this $coll xor'd together
* @group Bitwise
*/
- final def xorR(): Bool = macro SourceInfoTransform.noArg
+ final def xorR: Bool = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def xorR(dummy: Int*): Bool = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, OrReduceOp)
@@ -599,7 +629,10 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
* @return a hardware [[Bool]] asserted if this $coll equals zero
* @group Bitwise
*/
- final def unary_! () : Bool = macro SourceInfoTransform.noArg
+ final def unary_! : Bool = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_! (dummy: Int*): Bool = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_unary_! (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) : Bool = this === 0.U(1.W)
@@ -639,7 +672,11 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
* @return an [[SInt]] equal to this $coll with an additional zero in its most significant bit
* @note The width of the returned [[SInt]] is `width of this` + `1`.
*/
- final def zext(): SInt = macro SourceInfoTransform.noArg
+ final def zext: SInt = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def zext(dummy: Int*): SInt = macro SourceInfoTransform.noArgDummy
+
/** @group SourceInfoTransformMacro */
def do_zext(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt =
pushOp(DefPrim(sourceInfo, SInt(width + 1), ConvertOp, ref))
@@ -716,7 +753,10 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
* $constantWidth
* @group Arithmetic
*/
- final def unary_- (): SInt = macro SourceInfoTransform.noArg
+ final def unary_- : SInt = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_-(dummy: Int*): SInt = macro SourceInfoTransform.noArgDummy
/** Unary negation (constant width)
*
@@ -724,12 +764,15 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
* $constantWidth
* @group Arithmetic
*/
- final def unary_-% (): SInt = macro SourceInfoTransform.noArg
+ final def unary_-% : SInt = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_-%(dummy: Int*): SInt = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
- def unary_- (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = 0.S - this
+ def do_unary_- (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = 0.S - this
/** @group SourceInfoTransformMacro */
- def unary_-% (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = 0.S -% this
+ def do_unary_-% (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = 0.S -% this
/** add (default - no growth) operator */
override def do_+ (that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt =
@@ -755,7 +798,7 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
final def * (that: UInt): SInt = macro SourceInfoTransform.thatArg
/** @group SourceInfoTransformMacro */
def do_* (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = {
- val thatToSInt = that.zext()
+ val thatToSInt = that.zext
val result = binop(sourceInfo, SInt(this.width + thatToSInt.width), TimesOp, thatToSInt)
result.tail(1).asSInt
}
@@ -876,10 +919,10 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
/** @group SourceInfoTransformMacro */
def do_=== (that: SInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, EqualOp, that)
-// final def abs(): UInt = macro SourceInfoTransform.noArg
+// final def abs(): UInt = macro SourceInfoTransform.noArgDummy
def do_abs(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = {
- Mux(this < 0.S, (-this), this)
+ Mux(this < 0.S, -this, this)
}
override def do_<< (that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt =
@@ -938,7 +981,10 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
sealed trait Reset extends Element with ToBoolable {
/** Casts this $coll to an [[AsyncReset]] */
- final def asAsyncReset(): AsyncReset = macro SourceInfoWhiteboxTransform.noArg
+ final def asAsyncReset: AsyncReset = macro SourceInfoWhiteboxTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def asAsyncReset(dummy: Int*): AsyncReset = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_asAsyncReset(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): AsyncReset
@@ -1124,7 +1170,10 @@ sealed class Bool() extends UInt(1.W) with Reset {
def do_&& (that: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this & that
/** Reinterprets this $coll as a clock */
- def asClock(): Clock = macro SourceInfoTransform.noArg
+ def asClock: Clock = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def asClock(dummy: Int*): Clock = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_asClock(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Clock = pushOp(DefPrim(sourceInfo, Clock(), AsClockOp, ref))
@@ -1220,7 +1269,10 @@ package experimental {
* $expandingWidth
* @group Arithmetic
*/
- final def unary_- (): FixedPoint = macro SourceInfoTransform.noArg
+ final def unary_- : FixedPoint = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_-(dummy: Int*): FixedPoint = macro SourceInfoTransform.noArgDummy
/** Unary negation (constant width)
*
@@ -1228,7 +1280,9 @@ package experimental {
* $constantWidth
* @group Arithmetic
*/
- final def unary_-% (): FixedPoint = macro SourceInfoTransform.noArg
+ final def unary_-% : FixedPoint = macro SourceInfoTransform.noArg
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_-%(dummy: Int*): FixedPoint = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def unary_- (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): FixedPoint = FixedPoint.fromBigInt(0) - this
@@ -1663,8 +1717,15 @@ package experimental {
}
}
- final def unary_-(): Interval = macro SourceInfoTransform.noArg
- final def unary_-%(): Interval = macro SourceInfoTransform.noArg
+ final def unary_- : Interval = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_-(dummy: Int*): Interval = macro SourceInfoTransform.noArgDummy
+
+ final def unary_-% : Interval = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def unary_-%(dummy: Int*): Interval = macro SourceInfoTransform.noArgDummy
def unary_-(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Interval = {
Interval.Zero - this
@@ -1779,7 +1840,7 @@ package experimental {
def do_=/= (that: Interval)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, NotEqualOp, that)
def do_=== (that: Interval)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, EqualOp, that)
- // final def abs(): UInt = macro SourceInfoTransform.noArg
+ // final def abs(): UInt = macro SourceInfoTransform.noArgDummy
def do_abs(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Interval = {
Mux(this < Interval.Zero, (Interval.Zero - this), this)
diff --git a/core/src/main/scala/chisel3/Clock.scala b/core/src/main/scala/chisel3/Clock.scala
index edb07908..0400697d 100644
--- a/core/src/main/scala/chisel3/Clock.scala
+++ b/core/src/main/scala/chisel3/Clock.scala
@@ -32,8 +32,12 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element
def toPrintable: Printable = PString("CLOCK")
/** Returns the contents of the clock wire as a [[Bool]]. */
- final def asBool(): Bool = macro SourceInfoTransform.noArg
- def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this.asUInt().asBool()
+ final def asBool: Bool = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def asBool(dummy: Int*): Bool = macro SourceInfoTransform.noArgDummy
+
+ def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this.asUInt.asBool
override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref))
private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index 32d83008..4ae29ce8 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -645,18 +645,28 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
}
}
- def isLit(): Boolean = litOption.isDefined
+ def isLit: Boolean = litOption.isDefined
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def isLit(dummy: Int*): Boolean = isLit
+
/**
* If this is a literal that is representable as bits, returns the value as a BigInt.
* If not a literal, or not representable as bits (for example, is or contains Analog), returns None.
*/
- def litOption(): Option[BigInt]
+ def litOption: Option[BigInt]
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def litOption(dummy: Int*): Option[BigInt] = litOption
/**
* Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
*/
- def litValue(): BigInt = litOption.get
+ def litValue: BigInt = litOption.get
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def litValue(dummy: Int*): BigInt = litValue
/** Returns the width, in bits, if currently known. */
final def getWidth: Int =
@@ -679,7 +689,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
/** @group SourceInfoTransformMacro */
def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
val thatCloned = Wire(that.cloneTypeFull)
- thatCloned.connectFromBits(this.asUInt())
+ thatCloned.connectFromBits(this.asUInt)
thatCloned
}
@@ -695,7 +705,10 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
* @note Aggregates are recursively packed with the first element appearing
* in the least-significant bits of the result.
*/
- final def asUInt(): UInt = macro SourceInfoTransform.noArg
+ final def asUInt: UInt = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def asUInt(dummy: Int*): UInt = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt
@@ -715,7 +728,7 @@ trait WireFactory {
val x = t.cloneTypeFull
// Bind each element of x to being a Wire
- x.bind(WireBinding(Builder.forcedUserModule, Builder.currentWhen()))
+ x.bind(WireBinding(Builder.forcedUserModule, Builder.currentWhen))
pushCommand(DefWire(sourceInfo, x))
if (!compileOptions.explicitInvalidate) {
diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala
index 183620b6..aeacf052 100644
--- a/core/src/main/scala/chisel3/Mem.scala
+++ b/core/src/main/scala/chisel3/Mem.scala
@@ -130,7 +130,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) extends H
t.cloneTypeFull, Node(this), dir, i.ref, Builder.forcedClock.ref)
).id
// Bind each element of port to being a MemoryPort
- port.bind(MemoryPortBinding(Builder.forcedUserModule, Builder.currentWhen()))
+ port.bind(MemoryPortBinding(Builder.forcedUserModule, Builder.currentWhen))
port
}
}
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 3ae48821..56dce4d5 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -39,7 +39,7 @@ object Module extends SourceInfoDoc {
// Save then clear clock and reset to prevent leaking scope, must be set again in the Module
val (saveClock, saveReset) = (Builder.currentClock, Builder.currentReset)
- val savePrefix = Builder.getPrefix()
+ val savePrefix = Builder.getPrefix
Builder.clearPrefix()
Builder.currentClock = None
Builder.currentReset = None
diff --git a/core/src/main/scala/chisel3/Num.scala b/core/src/main/scala/chisel3/Num.scala
index 6dd299f4..219e18f4 100644
--- a/core/src/main/scala/chisel3/Num.scala
+++ b/core/src/main/scala/chisel3/Num.scala
@@ -148,7 +148,10 @@ trait Num[T <: Data] {
* $unchangedWidth
* @group Arithmetic
*/
- final def abs(): T = macro SourceInfoTransform.noArg
+ final def abs: T = macro SourceInfoTransform.noArg
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ final def abs(dummy: Int*): T = macro SourceInfoTransform.noArgDummy
/** @group SourceInfoTransformMacro */
def do_abs(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala
index bd9e5311..122c5ebd 100644
--- a/core/src/main/scala/chisel3/Reg.scala
+++ b/core/src/main/scala/chisel3/Reg.scala
@@ -41,7 +41,7 @@ object Reg {
val reg = t.cloneTypeFull
val clock = Node(Builder.forcedClock)
- reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen()))
+ reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen))
pushCommand(DefReg(sourceInfo, reg, clock))
reg
}
@@ -174,7 +174,7 @@ object RegInit {
val clock = Builder.forcedClock
val reset = Builder.forcedReset
- reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen()))
+ reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen))
requireIsHardware(init, "reg initializer")
pushCommand(DefRegInit(sourceInfo, reg, clock.ref, reset.ref, init.ref))
reg
diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala
index da6fc802..5c86efd3 100644
--- a/core/src/main/scala/chisel3/SeqUtils.scala
+++ b/core/src/main/scala/chisel3/SeqUtils.scala
@@ -81,7 +81,7 @@ private[chisel3] object SeqUtils {
val output = cloneSupertype(in.toSeq map { _._2}, "oneHotMux")
def buildAndOrMultiplexor[TT <: Data](inputs: Iterable[(Bool, TT)]): T = {
- val masked = for ((s, i) <- inputs) yield Mux(s, i.asUInt(), 0.U)
+ val masked = for ((s, i) <- inputs) yield Mux(s, i.asUInt, 0.U)
masked.reduceLeft(_ | _).asTypeOf(output)
}
diff --git a/core/src/main/scala/chisel3/StrongEnum.scala b/core/src/main/scala/chisel3/StrongEnum.scala
index b3d7cf7d..9ae4c889 100644
--- a/core/src/main/scala/chisel3/StrongEnum.scala
+++ b/core/src/main/scala/chisel3/StrongEnum.scala
@@ -246,7 +246,7 @@ abstract class EnumFactory {
private val enumRecords = mutable.ArrayBuffer.empty[EnumRecord]
private def enumNames = enumRecords.map(_.name).toSeq
- private def enumValues = enumRecords.map(_.inst.litValue()).toSeq
+ private def enumValues = enumRecords.map(_.inst.litValue).toSeq
private def enumInstances = enumRecords.map(_.inst).toSeq
private[chisel3] val enumTypeName = getClass.getName.init
@@ -265,7 +265,7 @@ abstract class EnumFactory {
def all: Seq[Type] = enumInstances
private[chisel3] def nameOfValue(id: BigInt): Option[String] = {
- enumRecords.find(_.inst.litValue() == id).map(_.name)
+ enumRecords.find(_.inst.litValue == id).map(_.name)
}
protected def Value: Type = macro EnumMacros.ValImpl
@@ -291,11 +291,11 @@ abstract class EnumFactory {
if (id.litOption.isEmpty) {
throwException(s"$enumTypeName defined with a non-literal type")
}
- if (id.litValue() < this.id) {
+ if (id.litValue < this.id) {
throwException(s"Enums must be strictly increasing: $enumTypeName")
}
- this.id = id.litValue()
+ this.id = id.litValue
do_Value(name)
}
diff --git a/core/src/main/scala/chisel3/When.scala b/core/src/main/scala/chisel3/When.scala
index a2c20d9a..ca383c0f 100644
--- a/core/src/main/scala/chisel3/When.scala
+++ b/core/src/main/scala/chisel3/When.scala
@@ -50,7 +50,7 @@ object when {
implicit val sourceInfo = UnlocatableSourceInfo
val whens = Builder.whenStack
whens.foldRight(true.B) {
- case (ctx, acc) => acc && ctx.localCond()
+ case (ctx, acc) => acc && ctx.localCond
}
}
}
@@ -81,7 +81,7 @@ final class WhenContext private[chisel3] (
private var scopeOpen = false
/** Returns the local condition, inverted for an otherwise */
- private[chisel3] def localCond(): Bool = {
+ private[chisel3] def localCond: Bool = {
implicit val compileOptions = ExplicitCompileOptions.Strict
implicit val sourceInfo = UnlocatableSourceInfo
val alt = altConds.foldRight(true.B) {
@@ -111,7 +111,10 @@ final class WhenContext private[chisel3] (
def otherwise(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit =
new WhenContext(sourceInfo, None, block, firrtlDepth + 1, cond ++: altConds)
- def active(): Boolean = scopeOpen
+ def active: Boolean = scopeOpen
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def active(dummy: Int*): Boolean = active
/*
*
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 441abc92..4e68623d 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -105,7 +105,7 @@ private[chisel3] trait HasId extends InstanceId {
private var auto_seed: Option[String] = None
// Prefix at time when this class is constructed
- private val construction_prefix: Prefix = Builder.getPrefix()
+ private val construction_prefix: Prefix = Builder.getPrefix
// Prefix when the latest [[suggestSeed]] or [[autoSeed]] is called
private var prefix_seed: Prefix = Nil
@@ -133,7 +133,7 @@ private[chisel3] trait HasId extends InstanceId {
private[chisel3] def forceAutoSeed(seed: String): this.type = {
auto_seed = Some(seed)
for(hook <- auto_postseed_hooks) { hook(seed) }
- prefix_seed = Builder.getPrefix()
+ prefix_seed = Builder.getPrefix
this
}
@@ -149,7 +149,7 @@ private[chisel3] trait HasId extends InstanceId {
*/
def suggestName(seed: =>String): this.type = {
if(suggested_seed.isEmpty) suggested_seed = Some(seed)
- prefix_seed = Builder.getPrefix()
+ prefix_seed = Builder.getPrefix
for(hook <- suggest_postseed_hooks) { hook(seed) }
this
}
@@ -485,7 +485,7 @@ private[chisel3] object Builder extends LazyLogging {
}
// Returns the prefix stack at this moment
- def getPrefix(): Prefix = chiselContext.get().prefixStack
+ def getPrefix: Prefix = chiselContext.get().prefixStack
def currentModule: Option[BaseModule] = dynamicContextVar.value match {
case Some(dyanmicContext) => dynamicContext.currentModule
@@ -572,7 +572,7 @@ private[chisel3] object Builder extends LazyLogging {
dynamicContext.whenStack = s
}
- def currentWhen(): Option[WhenContext] = dynamicContext.whenStack.headOption
+ def currentWhen: Option[WhenContext] = dynamicContext.whenStack.headOption
def currentClock: Option[Clock] = dynamicContext.currentClock
def currentClock_=(newClock: Option[Clock]): Unit = {
@@ -615,7 +615,7 @@ private[chisel3] object Builder extends LazyLogging {
}
def pushOp[T <: Data](cmd: DefPrim[T]): T = {
// Bind each element of the returned Data to being a Op
- cmd.id.bind(OpBinding(forcedUserModule, currentWhen()))
+ cmd.id.bind(OpBinding(forcedUserModule, currentWhen))
pushCommand(cmd).id
}
diff --git a/core/src/main/scala/chisel3/internal/prefix.scala b/core/src/main/scala/chisel3/internal/prefix.scala
index 9dc14901..620d0864 100644
--- a/core/src/main/scala/chisel3/internal/prefix.scala
+++ b/core/src/main/scala/chisel3/internal/prefix.scala
@@ -51,7 +51,7 @@ private[chisel3] object prefix { // scalastyle:ignore
// This causes extra prefixes to be added, and subsequently cleared in the
// Module constructor. Thus, we need to just make sure if the previous push
// was an incorrect one, to not pop off an empty stack
- if(Builder.getPrefix().nonEmpty) Builder.popPrefix()
+ if(Builder.getPrefix.nonEmpty) Builder.popPrefix()
ret
}
}
@@ -77,7 +77,7 @@ private[chisel3] object noPrefix {
* @return The return value of the provided function
*/
def apply[T](f: => T): T = {
- val prefix = Builder.getPrefix()
+ val prefix = Builder.getPrefix
Builder.clearPrefix()
val ret = f
Builder.setPrefix(prefix)
diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index 64cfa8b9..68e482dd 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -50,10 +50,18 @@ package object chisel3 {
/** Int to UInt conversion, recommended style for variables.
*/
- def asUInt(): UInt = UInt.Lit(bigint, Width())
+ def asUInt: UInt = UInt.Lit(bigint, Width())
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def asUInt(dummy: Int*): UInt = asUInt
+
/** Int to SInt conversion, recommended style for variables.
*/
- def asSInt(): SInt = SInt.Lit(bigint, Width())
+ def asSInt: SInt = SInt.Lit(bigint, Width())
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def asSInt(dummy: Int*): SInt = asSInt
+
/** Int to UInt conversion with specified width, recommended style for variables.
*/
def asUInt(width: Width): UInt = UInt.Lit(bigint, width)
@@ -68,17 +76,21 @@ package object chisel3 {
implicit class fromStringToLiteral(str: String) {
/** String to UInt parse, recommended style for constants.
*/
- def U: UInt = str.asUInt()
+ def U: UInt = str.asUInt
/** String to UInt parse with specified width, recommended style for constants.
*/
def U(width: Width): UInt = str.asUInt(width)
/** String to UInt parse, recommended style for variables.
*/
- def asUInt(): UInt = {
+ def asUInt: UInt = {
val bigInt = parse(str)
UInt.Lit(bigInt, Width(bigInt.bitLength max 1))
}
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def asUInt(dummy: Int*): UInt = asUInt
+
/** String to UInt parse with specified width, recommended style for variables.
*/
def asUInt(width: Width): UInt = UInt.Lit(parse(str), width)
@@ -107,7 +119,10 @@ package object chisel3 {
/** Boolean to Bool conversion, recommended style for variables.
*/
- def asBool(): Bool = Bool.Lit(boolean)
+ def asBool: Bool = Bool.Lit(boolean)
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def asBool(dummy: Int*): Bool = asBool
}
// Fixed Point is experimental for now, but we alias the implicit conversion classes here
diff --git a/macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala b/macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
index a8a7e8d5..ac3e236c 100644
--- a/macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
+++ b/macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
@@ -165,7 +165,12 @@ object SourceInfoTransform
class SourceInfoTransform(val c: Context) extends AutoSourceTransform {
import c.universe._
- def noArg(): c.Tree = {
+ def noArg: c.Tree = {
+ q"$thisObj.$doFuncTerm($implicitSourceInfo, $implicitCompileOptions)"
+ }
+
+ /** Necessary for dummy methods to auto-apply their arguments to this macro */
+ def noArgDummy(dummy: c.Tree*): c.Tree = {
q"$thisObj.$doFuncTerm($implicitSourceInfo, $implicitCompileOptions)"
}
@@ -224,7 +229,12 @@ object SourceInfoWhiteboxTransform
class SourceInfoWhiteboxTransform(val c: whitebox.Context) extends AutoSourceTransform {
import c.universe._
- def noArg(): c.Tree = {
+ def noArg: c.Tree = {
+ q"$thisObj.$doFuncTerm($implicitSourceInfo, $implicitCompileOptions)"
+ }
+
+ /** Necessary for dummy methods to auto-apply their arguments to this macro */
+ def noArgDummy(dummy: c.Tree*): c.Tree = {
q"$thisObj.$doFuncTerm($implicitSourceInfo, $implicitCompileOptions)"
}
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index dde2321d..ffbb7e27 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -33,7 +33,10 @@ package object Chisel {
implicit class AddDirectionToData[T<:Data](target: T) {
def asInput: T = Input(target)
def asOutput: T = Output(target)
- def flip(): T = Flipped(target)
+ def flip: T = Flipped(target)
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def flip(dummy: Int*): T = flip
}
implicit class AddDirMethodToData[T<:Data](target: T) {
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 0e05d114..060a684c 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -37,7 +37,10 @@ object ReadyValidIO {
/** Indicates if IO is both ready and valid
*/
- def fire(): Bool = target.ready && target.valid
+ def fire: Bool = target.ready && target.valid
+
+ @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+ def fire(dummy: Int = 0): Bool = fire
/** Push dat onto the output bits of this interface to let the consumer know it has happened.
* @param dat the values to assign to bits.
@@ -222,8 +225,8 @@ class Queue[T <: Data](val gen: T,
val ptr_match = enq_ptr.value === deq_ptr.value
val empty = ptr_match && !maybe_full
val full = ptr_match && maybe_full
- val do_enq = WireDefault(io.enq.fire())
- val do_deq = WireDefault(io.deq.fire())
+ val do_enq = WireDefault(io.enq.fire)
+ val do_deq = WireDefault(io.deq.fire)
val flush = io.flush.getOrElse(false.B)
// when flush is high, empty the queue
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index f2e238e9..222d0ba7 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -44,7 +44,7 @@ class SIntOps extends Module {
io.noteqout := (a =/= b)
io.lesseqout := a <= b
io.greateqout := a >= b
- // io.negout := -a(15, 0).toSInt
+ io.negout := -a(15, 0).asSInt
io.negout := (0.S -% a)
}
diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala
index d7dea571..404c3f66 100644
--- a/src/test/scala/chiselTests/StrongEnum.scala
+++ b/src/test/scala/chiselTests/StrongEnum.scala
@@ -257,8 +257,8 @@ class IsLitTester extends BasicTester {
for (e <- EnumExample.all) {
val wire = WireDefault(e)
- assert(e.isLit())
- assert(!wire.isLit())
+ assert(e.isLit)
+ assert(!wire.isLit)
}
stop()
}
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
index d91cd2f4..74d8c005 100644
--- a/src/test/scala/chiselTests/VecLiteralSpec.scala
+++ b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -142,17 +142,17 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
"lowest of vec literal contains least significant bits and " in {
val y = Vec(4, UInt(8.W)).Lit(0 -> 0xAB.U(8.W), 1 -> 0xCD.U(8.W), 2 -> 0xEF.U(8.W), 3 -> 0xFF.U(8.W))
- y.litValue() should be(BigInt("FFEFCDAB", 16))
+ y.litValue should be(BigInt("FFEFCDAB", 16))
}
"the order lits are specified does not matter" in {
val y = Vec(4, UInt(8.W)).Lit(3 -> 0xFF.U(8.W), 2 -> 0xEF.U(8.W), 1 -> 0xCD.U(8.W), 0 -> 0xAB.U(8.W))
- y.litValue() should be(BigInt("FFEFCDAB", 16))
+ y.litValue should be(BigInt("FFEFCDAB", 16))
}
"regardless of the literals widths, packing should be done based on the width of the Vec's gen" in {
val z = Vec(4, UInt(8.W)).Lit(0 -> 0x2.U, 1 -> 0x2.U, 2 -> 0x2.U, 3 -> 0x3.U)
- z.litValue() should be(BigInt("03020202", 16))
+ z.litValue should be(BigInt("03020202", 16))
}
"packing sparse vec lits should not pack, litOption returns None" in {
@@ -221,7 +221,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
chisel3.assert(outsideVecLit(2) === 0xBB.U)
chisel3.assert(outsideVecLit(3) === 0xAA.U)
- chisel3.assert(outsideVecLit.litValue().U === outsideVecLit.asUInt())
+ chisel3.assert(outsideVecLit.litValue.U === outsideVecLit.asUInt())
val insideVecLit = Vec(4, UInt(16.W)).Lit(0 -> 0xDD.U, 1 -> 0xCC.U, 2 -> 0xBB.U, 3 -> 0xAA.U)
chisel3.assert(insideVecLit(0) === 0xDD.U)
@@ -277,15 +277,15 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
1 -> Vec(3, UInt(4.W)).Lit(0 -> 4.U, 1 -> 5.U, 2 -> 6.U)
)
- outerVec.litValue() should be (BigInt("654321", 16))
- outerVec(0).litValue() should be (BigInt("321", 16))
- outerVec(1).litValue() should be (BigInt("654", 16))
- outerVec(0)(0).litValue() should be (BigInt(1))
- outerVec(0)(1).litValue() should be (BigInt(2))
- outerVec(0)(2).litValue() should be (BigInt(3))
- outerVec(1)(0).litValue() should be (BigInt(4))
- outerVec(1)(1).litValue() should be (BigInt(5))
- outerVec(1)(2).litValue() should be (BigInt(6))
+ outerVec.litValue should be (BigInt("654321", 16))
+ outerVec(0).litValue should be (BigInt("321", 16))
+ outerVec(1).litValue should be (BigInt("654", 16))
+ outerVec(0)(0).litValue should be (BigInt(1))
+ outerVec(0)(1).litValue should be (BigInt(2))
+ outerVec(0)(2).litValue should be (BigInt(3))
+ outerVec(1)(0).litValue should be (BigInt(4))
+ outerVec(1)(1).litValue should be (BigInt(5))
+ outerVec(1)(2).litValue should be (BigInt(6))
}
"contained vecs should work" in {
@@ -473,19 +473,19 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
0 -> (new SubBundle).Lit(_.foo -> 0xab.U, _.bar -> 0xc.U),
1 -> (new SubBundle).Lit(_.foo -> 0xde.U, _.bar -> 0xf.U)
)
- vec.litValue().toString(16) should be("defabc")
+ vec.litValue.toString(16) should be("defabc")
}
"vec literals can have bundle children assembled incrementally" in {
val bundle1 = (new SubBundle).Lit(_.foo -> 0xab.U, _.bar -> 0xc.U)
val bundle2 = (new SubBundle).Lit(_.foo -> 0xde.U, _.bar -> 0xf.U)
- bundle1.litValue().toString(16) should be("abc")
- bundle2.litValue().toString(16) should be("def")
+ bundle1.litValue.toString(16) should be("abc")
+ bundle2.litValue.toString(16) should be("def")
val vec = Vec(2, new SubBundle).Lit(0 -> bundle1, 1 -> bundle2)
- vec.litValue().toString(16) should be("defabc")
+ vec.litValue.toString(16) should be("defabc")
}
"bundles can contain vec lits" in {
@@ -495,7 +495,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
val foo = Vec(3, UInt(4.W))
val bar = Vec(2, UInt(4.W))
}).Lit(_.foo -> vec1, _.bar -> vec2)
- bundle.litValue().toString(16) should be("cbaed")
+ bundle.litValue.toString(16) should be("cbaed")
}
"bundles can contain vec lits in-line" in {
@@ -506,21 +506,21 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
_.foo -> Vec(3, UInt(4.W)).Lit(0 -> 0xa.U, 1 -> 0xb.U, 2 -> 0xc.U),
_.bar -> Vec(2, UInt(4.W)).Lit(0 -> 0xd.U, 1 -> 0xe.U)
)
- bundle.litValue().toString(16) should be("cbaed")
+ bundle.litValue.toString(16) should be("cbaed")
}
"Vec.Lit is a trivial Vec literal factory" in {
val vec = Vec.Lit(0xa.U, 0xb.U)
- vec(0).litValue() should be(0xa)
- vec(1).litValue() should be(0xb)
+ vec(0).litValue should be(0xa)
+ vec(1).litValue should be(0xb)
}
"Vec.Lit bases it's element width on the widest literal supplied" in {
val vec = Vec.Lit(0xa.U, 0xbbbb.U)
- vec(0).litValue() should be(0xa)
- vec(1).litValue() should be(0xbbbb)
+ vec(0).litValue should be(0xa)
+ vec(1).litValue should be(0xbbbb)
vec.length should be(2)
vec.getWidth should be(16 * 2)
- vec.litValue() should be(BigInt("bbbb000a", 16))
+ vec.litValue should be(BigInt("bbbb000a", 16))
}
}