Merge pull request #1175 from freechipsproject/bore-name

Internal BoringUtils.bore Bug Fix

1 files changed, 17 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
index 856f6b91..755ba60b 100644
--- a/src/test/scala/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala
@@ -106,4 +106,21 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
       .getMessage should startWith ("Unable to determine source mapping for sink")
   }
 
+  class InternalBore extends RawModule {
+    val in = IO(Input(Bool()))
+    val out = IO(Output(Bool()))
+    out := false.B
+    BoringUtils.bore(in, Seq(out))
+  }
+
+  class InternalBoreTester extends ShouldntAssertTester {
+    val dut = Module(new InternalBore)
+    dut.in := true.B
+    chisel3.assert(dut.out === true.B)
+  }
+
+  it should "work for an internal (same module) BoringUtils.bore" in {
+    runTester(new InternalBoreTester) should be (true)
+  }
+
 }