diff options
| author | Jack Koenig | 2019-04-24 13:07:14 -0700 |
|---|---|---|
| committer | GitHub | 2019-04-24 13:07:14 -0700 |
| commit | 5e4c3be862bf53ad34315e635d89816729550c01 (patch) | |
| tree | fb19247f089cc17f8aeb4e779fa4839ef0596110 /src/test | |
| parent | 9bef2461e55c724354f20bce0d32c7f5e6ac45ff (diff) | |
Add back Int forms of Mem do_apply methods (#1082)
This is necessary to support code that imports an implicit conversion
from Int to UInt
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/Mem.scala | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala index 176ea5e7..ebdb1483 100644 --- a/src/test/scala/chiselTests/Mem.scala +++ b/src/test/scala/chiselTests/Mem.scala @@ -93,4 +93,16 @@ class MemorySpec extends ChiselPropSpec { val cmem = compile(new HugeCMemTester(size)) cmem should include (s"reg /* sparse */ [7:0] mem [0:$addrWidth'd${size-1}];") } + + property("Implicit conversions with Mem indices should work") { + """ + |import chisel3._ + |import chisel3.util.ImplicitConversions._ + |class MyModule extends Module { + | val io = IO(new Bundle {}) + | val mem = Mem(32, UInt(8.W)) + | mem(0) := 0.U + |} + |""".stripMargin should compile + } } |
