diff options
| author | mergify[bot] | 2022-09-27 19:36:39 +0000 |
|---|---|---|
| committer | GitHub | 2022-09-27 19:36:39 +0000 |
| commit | f19556801137091fa79a6d79395985474527b72d (patch) | |
| tree | a3727f78e6cac8a57531e47b16d827009f0649ca /src/test/scala | |
| parent | c11eead29545799baf8c57e8c1b8b7351b98a258 (diff) | |
Use Treadle (on pull requests only) to speed up CI (backport #2341) (#2748)
* Support using Treadle for 'sbt test'
Treadle will be used as the "defaultBackend" when the environment
variable CHISEL3_CI_USE_TREADLE is set. The intent is to set this
variable during CI for pre-merge CI (aka on pull requests).
(cherry picked from commit 7d39b7bd2b6f38dac90fe25064744ffc0ada0fe4)
* Use Treadle for CI on pull requests
(cherry picked from commit 82660673e56a816e68fcc068e3e04e127f076faf)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala')
| -rw-r--r-- | src/test/scala/chiselTests/ChiselSpec.scala | 5 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 4 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index 6f560b94..e00afcf6 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -38,7 +38,10 @@ trait ChiselRunners extends Assertions with BackendCompilationUtilities { annotations: AnnotationSeq = Seq() ): Boolean = { // Change this to enable Treadle as a backend - val defaultBackend = chisel3.testers.TesterDriver.defaultBackend + val defaultBackend = { + val useTreadle = sys.env.get("CHISEL3_CI_USE_TREADLE").isDefined + if (useTreadle) chisel3.testers.TreadleBackend else chisel3.testers.TesterDriver.defaultBackend + } val hasBackend = TestUtils.containsBackend(annotations) val annos: Seq[Annotation] = if (hasBackend) annotations else defaultBackend +: annotations TesterDriver.execute(() => t, additionalVResources, annos) diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 02743187..4a871890 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -6,7 +6,7 @@ import org.scalacheck._ import chisel3._ import chisel3.stage.ChiselStage -import chisel3.testers.BasicTester +import chisel3.testers.{BasicTester, TesterDriver} import chisel3.util._ import org.scalacheck.Shrink import scala.annotation.tailrec @@ -456,7 +456,7 @@ class VecSpec extends ChiselPropSpec with Utils { } property("Infering widths on huge Vecs should not cause a stack overflow") { - assertTesterPasses { new HugeVecTester(10000) } + assertTesterPasses(new HugeVecTester(10000), annotations = TesterDriver.verilatorOnly) } property("A Reg of a Vec of a single 1 bit element should compile and work") { |
