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authorJack Koenig2020-02-10 12:28:06 -0800
committerGitHub2020-02-10 20:28:06 +0000
commit9a209b82022a18542260715bc7db777f68ab079f (patch)
tree69baa49e59988b6eba3d1a4616e153fb01d2d202 /src/test/scala/chiselTests
parent355d11eab572a28b6e010fbb8b13bc1568f5603a (diff)
Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/test/scala/chiselTests')
-rw-r--r--src/test/scala/chiselTests/PrintableSpec.scala10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index aeb92532..4ecc073e 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -95,6 +95,16 @@ class PrintableSpec extends FlatSpec with Matchers {
case e => fail()
}
}
+ it should "correctly emit tab" in {
+ class MyModule extends BasicTester {
+ printf(p"\t")
+ }
+ val firrtl = Driver.emit(() => new MyModule)
+ getPrintfs(firrtl) match {
+ case Seq(Printf("\\t", Seq())) =>
+ case e => fail()
+ }
+ }
it should "support names of circuit elements including submodule IO" in {
// Submodule IO is a subtle issue because the Chisel element has a different
// parent module