diff options
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/Printf.scala | 6 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/PrintableSpec.scala | 10 |
2 files changed, 14 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Printf.scala b/chiselFrontend/src/main/scala/chisel3/Printf.scala index b80d5eb5..0478e889 100644 --- a/chiselFrontend/src/main/scala/chisel3/Printf.scala +++ b/chiselFrontend/src/main/scala/chisel3/Printf.scala @@ -19,13 +19,15 @@ object printf { // scalastyle:ignore object.name require(formatIn forall (c => c.toInt > 0 && c.toInt < 128), "format strings must comprise non-null ASCII values") def escaped(x: Char) = { - require(x.toInt >= 0) + require(x.toInt >= 0, s"char ${x} to Int ${x.toInt} must be >= 0") if (x == '"' || x == '\\') { s"\\${x}" } else if (x == '\n') { "\\n" + } else if (x == '\t') { + "\\t" } else { - require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved + require(x.toInt >= 32, s"char ${x} to Int ${x.toInt} must be >= 32") // TODO \xNN once FIRRTL issue #59 is resolved x } } diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index aeb92532..4ecc073e 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -95,6 +95,16 @@ class PrintableSpec extends FlatSpec with Matchers { case e => fail() } } + it should "correctly emit tab" in { + class MyModule extends BasicTester { + printf(p"\t") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("\\t", Seq())) => + case e => fail() + } + } it should "support names of circuit elements including submodule IO" in { // Submodule IO is a subtle issue because the Chisel element has a different // parent module |