Fix bug where refs may not get set for Records (#1645)

This requires a combination of things, but it happens to be a
combination used by Diplomacy in Rocket Chip. It must be a Record in
compatibility code with Vecs as fields and a mix of components with and
without set directions.

1 files changed, 18 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index f3799613..50213d4d 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -8,6 +8,8 @@ import chisel3.testers.BasicTester
 import org.scalacheck.Gen
 import org.scalatestplus.scalacheck.ScalaCheckDrivenPropertyChecks
 
+import scala.collection.immutable.ListMap
+
 // Need separate import to override compile options from Chisel._
 object CompatibilityCustomCompileOptions {
   import Chisel.{defaultCompileOptions => _, _}
@@ -578,4 +580,20 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     result.compileOptions should be theSameInstanceAs (customCompileOptions)
   }
 
+  it should "properly set the refs of Records" in {
+    class MyRecord extends Record {
+      val foo = Vec(1, Bool()).asInput
+      val bar = Vec(1, Bool())
+      val elements = ListMap("in" -> foo, "out" -> bar)
+      def cloneType = (new MyRecord).asInstanceOf[this.type]
+    }
+    class Foo extends Module {
+      val io = IO(new MyRecord)
+      io.bar := io.foo
+    }
+    val verilog = ChiselStage.emitVerilog(new Foo)
+    // Check that the names are correct (and that the FIRRTL is valid)
+    verilog should include ("assign io_out_0 = io_in_0;")
+  }
+
 }