diff options
| -rw-r--r-- | core/src/main/scala/chisel3/Aggregate.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilitySpec.scala | 18 |
2 files changed, 19 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala index 6c11b2db..e45f5b46 100644 --- a/core/src/main/scala/chisel3/Aggregate.scala +++ b/core/src/main/scala/chisel3/Aggregate.scala @@ -493,7 +493,6 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection): Unit = { try { super.bind(target, parentDirection) - setElementRefs() } catch { // nasty compatibility mode shim, where anything flies case e: MixedDirectionAggregateException if !compileOptions.dontAssumeDirectionality => val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection) @@ -503,6 +502,7 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio case _ => ActualDirection.Bidirectional(ActualDirection.Default) } } + setElementRefs() } /** Creates a Bundle literal of this type with specified values. this must be a chisel type. diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index f3799613..50213d4d 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -8,6 +8,8 @@ import chisel3.testers.BasicTester import org.scalacheck.Gen import org.scalatestplus.scalacheck.ScalaCheckDrivenPropertyChecks +import scala.collection.immutable.ListMap + // Need separate import to override compile options from Chisel._ object CompatibilityCustomCompileOptions { import Chisel.{defaultCompileOptions => _, _} @@ -578,4 +580,20 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck result.compileOptions should be theSameInstanceAs (customCompileOptions) } + it should "properly set the refs of Records" in { + class MyRecord extends Record { + val foo = Vec(1, Bool()).asInput + val bar = Vec(1, Bool()) + val elements = ListMap("in" -> foo, "out" -> bar) + def cloneType = (new MyRecord).asInstanceOf[this.type] + } + class Foo extends Module { + val io = IO(new MyRecord) + io.bar := io.foo + } + val verilog = ChiselStage.emitVerilog(new Foo) + // Check that the names are correct (and that the FIRRTL is valid) + verilog should include ("assign io_out_0 = io_in_0;") + } + } |