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authorJack Koenig2022-01-10 10:39:52 -0800
committerJack Koenig2022-01-10 15:53:55 -0800
commit3131c0daad41dea78bede4517669e376c41a325a (patch)
tree55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/experimental/ForceNames.scala
parentdd36f97a82746cec0b25b94651581fe799e24579 (diff)
Apply scalafmt
Command: sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/experimental/ForceNames.scala')
-rw-r--r--src/test/scala/chiselTests/experimental/ForceNames.scala13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/experimental/ForceNames.scala b/src/test/scala/chiselTests/experimental/ForceNames.scala
index 06f911e6..233b4a5f 100644
--- a/src/test/scala/chiselTests/experimental/ForceNames.scala
+++ b/src/test/scala/chiselTests/experimental/ForceNames.scala
@@ -6,7 +6,7 @@ import firrtl._
import chisel3._
import chisel3.experimental.annotate
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
-import chisel3.util.experimental.{ForceNameAnnotation, ForceNamesTransform, InlineInstance, forceName}
+import chisel3.util.experimental.{forceName, ForceNameAnnotation, ForceNamesTransform, InlineInstance}
import firrtl.annotations.{Annotation, ReferenceTarget}
import firrtl.options.{Dependency, TargetDirAnnotation}
import firrtl.stage.RunFirrtlTransformAnnotation
@@ -61,7 +61,12 @@ object ForceNamesHierarchy {
class ForceNamesSpec extends ChiselFlatSpec {
- def run[T <: RawModule](dut: => T, testName: String, inputAnnos: Seq[Annotation] = Nil, info: LogLevel.Value = LogLevel.None): Iterable[String] = {
+ def run[T <: RawModule](
+ dut: => T,
+ testName: String,
+ inputAnnos: Seq[Annotation] = Nil,
+ info: LogLevel.Value = LogLevel.None
+ ): Iterable[String] = {
def stage = new ChiselStage {
override val targets = Seq(
Dependency[chisel3.stage.phases.Elaborate],
@@ -85,11 +90,11 @@ class ForceNamesSpec extends ChiselFlatSpec {
}
"Force Names on a wrapping instance" should "work" in {
val verilog = run(new ForceNamesHierarchy.WrapperExample, "wrapper")
- exactly(1, verilog) should include ("MyLeaf inst")
+ exactly(1, verilog) should include("MyLeaf inst")
}
"Force Names on an instance port" should "work" in {
val verilog = run(new ForceNamesHierarchy.RenamePortsExample, "instports")
- atLeast(1, verilog) should include ("input [2:0] inn")
+ atLeast(1, verilog) should include("input [2:0] inn")
}
"Force Names with a conflicting name" should "error" in {
intercept[CustomTransformException] {