Apply scalafmt

Command:
sbt scalafmtAll

13 files changed, 433 insertions, 349 deletions

diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index 7c5d170b..5ef062fa 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -54,7 +54,7 @@ object FlatDecoupledDataView {
 
 class DataViewSpec extends ChiselFlatSpec {
 
-  behavior of "DataView"
+  behavior.of("DataView")
 
   it should "support simple Bundle viewing" in {
     import SimpleBundleDataView._
@@ -240,8 +240,8 @@ class DataViewSpec extends ChiselFlatSpec {
       fooOut := cat
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    chirrtl should include ("node cat = cat(barIn.foo, barIn.bar)")
-    chirrtl should include ("fooOut <= cat")
+    chirrtl should include("node cat = cat(barIn.foo, barIn.bar)")
+    chirrtl should include("fooOut <= cat")
   }
 
   it should "be composable" in {
@@ -262,8 +262,8 @@ class DataViewSpec extends ChiselFlatSpec {
       z := b.viewAs[Bar].viewAs[Fizz]
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    chirrtl should include ("y.fizz <= a.foo")
-    chirrtl should include ("z.fizz <= b.foo")
+    chirrtl should include("y.fizz <= a.foo")
+    chirrtl should include("z.fizz <= b.foo")
   }
 
   it should "enable using Seq like Data" in {
@@ -277,8 +277,8 @@ class DataViewSpec extends ChiselFlatSpec {
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign y = sel ? a : c;")
-    verilog should include ("assign z = sel ? b : d;")
+    verilog should include("assign y = sel ? a : c;")
+    verilog should include("assign z = sel ? b : d;")
   }
 
   // This example should be turned into a built-in feature
@@ -291,9 +291,9 @@ class DataViewSpec extends ChiselFlatSpec {
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign x = a;")
-    verilog should include ("assign y = b;")
-    verilog should include ("assign z = c;")
+    verilog should include("assign x = a;")
+    verilog should include("assign y = b;")
+    verilog should include("assign z = c;")
   }
 
   it should "support recursive composition of views" in {
@@ -307,10 +307,10 @@ class DataViewSpec extends ChiselFlatSpec {
       Seq((w, x), (y, z)) := VecInit[HWTuple2[UInt, UInt]]((a, b), (c, d))
     }
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign w = a;")
-    verilog should include ("assign x = b;")
-    verilog should include ("assign y = c;")
-    verilog should include ("assign z = d;")
+    verilog should include("assign w = a;")
+    verilog should include("assign x = b;")
+    verilog should include("assign y = c;")
+    verilog should include("assign z = d;")
   }
 
   it should "support dynamic indexing for Vec identity views" in {
@@ -328,8 +328,8 @@ class DataViewSpec extends ChiselFlatSpec {
       dataOut := selected
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    chirrtl should include ("vec[addr] <= dataIn")
-    chirrtl should include ("dataOut <= vec[addr]")
+    chirrtl should include("vec[addr] <= dataIn")
+    chirrtl should include("dataOut <= vec[addr]")
   }
 
   it should "error if you try to dynamically index a Vec view that does not correspond to a Vec target" in {
@@ -346,9 +346,9 @@ class DataViewSpec extends ChiselFlatSpec {
       selected := (inA, inB)
       (outA, outB) := selected
     }
-    (the [InvalidViewException] thrownBy {
+    (the[InvalidViewException] thrownBy {
       ChiselStage.emitChirrtl(new MyModule)
-    }).getMessage should include ("Dynamic indexing of Views is not yet supported")
+    }).getMessage should include("Dynamic indexing of Views is not yet supported")
   }
 
   it should "error if the mapping is non-total in the view" in {
@@ -360,8 +360,8 @@ class DataViewSpec extends ChiselFlatSpec {
       val out = IO(Output(tpe))
       out := in.viewAs[MyBundle]
     }
-    val err = the [InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
-    err.toString should include ("View field '_.foo' is missing")
+    val err = the[InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
+    err.toString should include("View field '_.foo' is missing")
   }
 
   it should "error if the mapping is non-total in the target" in {
@@ -371,8 +371,8 @@ class DataViewSpec extends ChiselFlatSpec {
       val out = IO(Output(UInt(8.W)))
       out := (a, b).viewAs[UInt]
     }
-    val err = the [InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
-    err.toString should include ("Target field '_._2' is missing")
+    val err = the[InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
+    err.toString should include("Target field '_._2' is missing")
   }
 
   it should "error if the mapping contains Data that are not part of the Target" in {
@@ -389,8 +389,8 @@ class DataViewSpec extends ChiselFlatSpec {
       val out = IO(Output(new BundleB))
       out := in.viewAs[BundleB]
     }
-    val err = the [InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
-    err.toString should include ("View mapping must only contain Elements within the Target")
+    val err = the[InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
+    err.toString should include("View mapping must only contain Elements within the Target")
   }
 
   it should "error if the mapping contains Data that are not part of the View" in {
@@ -408,8 +408,8 @@ class DataViewSpec extends ChiselFlatSpec {
       val out = IO(Output(new BundleB))
       out.viewAs[BundleA] := in
     }
-    val err = the [InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
-    err.toString should include ("View mapping must only contain Elements within the View")
+    val err = the[InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
+    err.toString should include("View mapping must only contain Elements within the View")
   }
 
   it should "error if a view has a width that does not match the target" in {
@@ -425,9 +425,9 @@ class DataViewSpec extends ChiselFlatSpec {
       val out = IO(Output(new BundleB))
       out := in.viewAs[BundleB]
     }
-    val err = the [InvalidViewException] thrownBy ChiselStage.emitChirrtl(new MyModule)
+    val err = the[InvalidViewException] thrownBy ChiselStage.emitChirrtl(new MyModule)
     val expected = """View field _\.bar UInt<4> has width <4> that is incompatible with target value .+'s width <8>""".r
-    err.getMessage should fullyMatch regex expected
+    (err.getMessage should fullyMatch).regex(expected)
   }
 
   it should "error if a view has a known width when the target width is unknown" in {
@@ -443,12 +443,13 @@ class DataViewSpec extends ChiselFlatSpec {
       val out = IO(Output(new BundleB))
       out := in.viewAs[BundleB]
     }
-    val err = the [InvalidViewException] thrownBy ChiselStage.emitChirrtl(new MyModule)
-    val expected = """View field _\.bar UInt<4> has width <4> that is incompatible with target value .+'s width <unknown>""".r
-    err.getMessage should fullyMatch regex expected
+    val err = the[InvalidViewException] thrownBy ChiselStage.emitChirrtl(new MyModule)
+    val expected =
+      """View field _\.bar UInt<4> has width <4> that is incompatible with target value .+'s width <unknown>""".r
+    (err.getMessage should fullyMatch).regex(expected)
   }
 
-  behavior of "PartialDataView"
+  behavior.of("PartialDataView")
 
   it should "still error if the mapping is non-total in the view" in {
     class MyBundle(val foo: UInt, val bar: UInt) extends Bundle
@@ -458,8 +459,8 @@ class DataViewSpec extends ChiselFlatSpec {
       val out = IO(Output(new MyBundle(UInt(8.W), UInt(8.W))))
       out := in.viewAs[MyBundle]
     }
-    val err = the [InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
-    err.toString should include ("View field '_.foo' is missing")
+    val err = the[InvalidViewException] thrownBy (ChiselStage.emitVerilog(new MyModule))
+    err.toString should include("View field '_.foo' is missing")
   }
 
   it should "NOT error if the mapping is non-total in the target" in {
@@ -470,6 +471,6 @@ class DataViewSpec extends ChiselFlatSpec {
       out := (a, b).viewAs[UInt]
     }
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign out = b;")
+    verilog should include("assign out = b;")
   }
 }
diff --git a/src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala b/src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala
index 3f149f75..4704a942 100644
--- a/src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala
+++ b/src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.experimental
 import chisel3._
 import chisel3.experimental.{BaseModule, ExtModule}
 import chisel3.experimental.dataview._
-import chisel3.util.{Decoupled, DecoupledIO, Queue, QueueIO, log2Ceil}
+import chisel3.util.{log2Ceil, Decoupled, DecoupledIO, Queue, QueueIO}
 import chiselTests.ChiselFlatSpec
 import firrtl.transforms.DontTouchAnnotation
 
@@ -52,6 +52,6 @@ class DataViewIntegrationSpec extends ChiselFlatSpec {
   "Users" should "be able to view and annotate Modules" in {
     val (_, annos) = getFirrtlAndAnnos(new MyModule)
     val ts = annos.collect { case DontTouchAnnotation(t) => t.serialize }
-    ts should equal (Seq("~MyModule|Queue>enq_ptr_value"))
+    ts should equal(Seq("~MyModule|Queue>enq_ptr_value"))
   }
 }
diff --git a/src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala b/src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala
index a17b0f40..da27c9c8 100644
--- a/src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala
+++ b/src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.experimental
 import chisel3._
 import chisel3.experimental.dataview._
 import chisel3.experimental.conversions._
-import chisel3.experimental.{ChiselAnnotation, annotate}
+import chisel3.experimental.{annotate, ChiselAnnotation}
 import chiselTests.ChiselFlatSpec
 
 object DataViewTargetSpec {
@@ -29,22 +29,22 @@ class DataViewTargetSpec extends ChiselFlatSpec {
     _.instanceName,
     _.pathName,
     _.parentPathName,
-    _.parentModName,
+    _.parentModName
   )
 
   // Check helpers
   private def checkAll(impl: Data, refs: String*): Unit = {
-    refs.size should be (checks.size)
+    refs.size should be(checks.size)
     for ((check, value) <- checks.zip(refs)) {
-      check(impl) should be (value)
+      check(impl) should be(value)
     }
   }
   private def checkSameAs(impl: Data, refs: Data*): Unit =
     for (ref <- refs) {
-      checkAll(impl, checks.map(_(ref)):_*)
+      checkAll(impl, checks.map(_(ref)): _*)
     }
 
-  behavior of "DataView Naming"
+  behavior.of("DataView Naming")
 
   it should "support views of Elements" in {
     class MyChild extends Module {
@@ -67,7 +67,8 @@ class DataViewTargetSpec extends ChiselFlatSpec {
       val foo = UInt(8.W)
       val bars = Vec(2, UInt(8.W))
     }
-    implicit val dv = DataView[MyBundle, Vec[UInt]](_ => Vec(3, UInt(8.W)), _.foo -> _(0), _.bars(0) -> _(1), _.bars(1) -> _(2))
+    implicit val dv =
+      DataView[MyBundle, Vec[UInt]](_ => Vec(3, UInt(8.W)), _.foo -> _(0), _.bars(0) -> _(1), _.bars(1) -> _(2))
     class MyChild extends Module {
       val out = IO(Output(new MyBundle))
       val outView = out.viewAs[Vec[UInt]] // Note different type
@@ -82,7 +83,7 @@ class DataViewTargetSpec extends ChiselFlatSpec {
       out := inst.out
     }
     val m = elaborateAndGetModule(new MyParent)
-    val outView = m.inst.out.viewAs[Vec[UInt]]// Note different type
+    val outView = m.inst.out.viewAs[Vec[UInt]] // Note different type
     val outFooView = m.inst.out.foo.viewAs[UInt]
     val outBarsView = m.inst.out.bars.viewAs[Vec[UInt]]
     val outBars0View = m.inst.out.bars(0).viewAs[UInt]
@@ -90,8 +91,15 @@ class DataViewTargetSpec extends ChiselFlatSpec {
     checkSameAs(m.inst.out, m.inst.outView, outView)
     checkSameAs(m.inst.out.foo, m.inst.outFooView, m.inst.outView(0), outFooView, outView(0))
     checkSameAs(m.inst.out.bars, m.inst.outBarsView, outBarsView)
-    checkSameAs(m.inst.out.bars(0), m.inst.outBars0View, outBars0View, m.inst.outView(1), outView(1),
-      m.inst.outBarsView(0), outBarsView(0))
+    checkSameAs(
+      m.inst.out.bars(0),
+      m.inst.outBars0View,
+      outBars0View,
+      m.inst.outView(1),
+      outView(1),
+      m.inst.outBarsView(0),
+      outBarsView(0)
+    )
   }
 
   // Ideally this would work 1:1 but that requires changing the binding
@@ -123,7 +131,7 @@ class DataViewTargetSpec extends ChiselFlatSpec {
       2 -> "~MyParent|MyParent/inst:MyChild>out.foo",
       3 -> "~MyParent|MyParent/inst:MyChild>out"
     )
-    pairs should equal (expected)
+    pairs should equal(expected)
   }
 
   it should "support annotating views that cannot be mapped to a single ReferenceTarget" in {
@@ -161,9 +169,9 @@ class DataViewTargetSpec extends ChiselFlatSpec {
       3 -> "~MyParent|MyParent/inst:MyChild>io.c",
       3 -> "~MyParent|MyParent/inst:MyChild>io.d",
       4 -> "~MyParent|MyChild>io.b",
-      4 -> "~MyParent|MyChild>io.d",
+      4 -> "~MyParent|MyChild>io.d"
     )
-    pairs should equal (expected)
+    pairs should equal(expected)
   }
 
   // TODO check these properties when using @instance API (especially preservation of totality)
diff --git a/src/test/scala/chiselTests/experimental/ForceNames.scala b/src/test/scala/chiselTests/experimental/ForceNames.scala
index 06f911e6..233b4a5f 100644
--- a/src/test/scala/chiselTests/experimental/ForceNames.scala
+++ b/src/test/scala/chiselTests/experimental/ForceNames.scala
@@ -6,7 +6,7 @@ import firrtl._
 import chisel3._
 import chisel3.experimental.annotate
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
-import chisel3.util.experimental.{ForceNameAnnotation, ForceNamesTransform, InlineInstance, forceName}
+import chisel3.util.experimental.{forceName, ForceNameAnnotation, ForceNamesTransform, InlineInstance}
 import firrtl.annotations.{Annotation, ReferenceTarget}
 import firrtl.options.{Dependency, TargetDirAnnotation}
 import firrtl.stage.RunFirrtlTransformAnnotation
@@ -61,7 +61,12 @@ object ForceNamesHierarchy {
 
 class ForceNamesSpec extends ChiselFlatSpec {
 
-  def run[T <: RawModule](dut: => T, testName: String, inputAnnos: Seq[Annotation] = Nil, info: LogLevel.Value = LogLevel.None): Iterable[String] = {
+  def run[T <: RawModule](
+    dut:        => T,
+    testName:   String,
+    inputAnnos: Seq[Annotation] = Nil,
+    info:       LogLevel.Value = LogLevel.None
+  ): Iterable[String] = {
     def stage = new ChiselStage {
       override val targets = Seq(
         Dependency[chisel3.stage.phases.Elaborate],
@@ -85,11 +90,11 @@ class ForceNamesSpec extends ChiselFlatSpec {
   }
   "Force Names on a wrapping instance" should "work" in {
     val verilog = run(new ForceNamesHierarchy.WrapperExample, "wrapper")
-    exactly(1, verilog) should include ("MyLeaf inst")
+    exactly(1, verilog) should include("MyLeaf inst")
   }
   "Force Names on an instance port" should "work" in {
     val verilog = run(new ForceNamesHierarchy.RenamePortsExample, "instports")
-    atLeast(1, verilog) should include ("input  [2:0] inn")
+    atLeast(1, verilog) should include("input  [2:0] inn")
   }
   "Force Names with a conflicting name" should "error" in {
     intercept[CustomTransformException] {
diff --git a/src/test/scala/chiselTests/experimental/GroupSpec.scala b/src/test/scala/chiselTests/experimental/GroupSpec.scala
index 52435ad8..5e0c34bb 100644
--- a/src/test/scala/chiselTests/experimental/GroupSpec.scala
+++ b/src/test/scala/chiselTests/experimental/GroupSpec.scala
@@ -16,9 +16,9 @@ import scala.collection.mutable
 
 class GroupSpec extends ChiselFlatSpec {
 
-  def collectInstances(c: fir.Circuit, top: Option[String] = None): Seq[String] = new InstanceGraph(c)
-    .fullHierarchy.values.flatten.toSeq
-    .map( v => (top.getOrElse(v.head.name) +: v.tail.map(_.name)).mkString(".") )
+  def collectInstances(c: fir.Circuit, top: Option[String] = None): Seq[String] =
+    new InstanceGraph(c).fullHierarchy.values.flatten.toSeq
+      .map(v => (top.getOrElse(v.head.name) +: v.tail.map(_.name)).mkString("."))
 
   def collectDeclarations(m: fir.DefModule): Set[String] = {
     val decs = mutable.HashSet[String]()
@@ -32,17 +32,16 @@ class GroupSpec extends ChiselFlatSpec {
 
   def lower[T <: RawModule](gen: () => T): fir.Circuit = {
     (new ChiselStage)
-      .execute(Array("--compiler", "low",
-                     "--target-dir", "test_run_dir"),
-               Seq(ChiselGeneratorAnnotation(gen)))
+      .execute(Array("--compiler", "low", "--target-dir", "test_run_dir"), Seq(ChiselGeneratorAnnotation(gen)))
       .collectFirst {
         case firrtl.stage.FirrtlCircuitAnnotation(circuit) => circuit
-      }.get
+      }
+      .get
   }
 
   "Module Grouping" should "compile to low FIRRTL" in {
     class MyModule extends Module {
-      val io = IO(new Bundle{
+      val io = IO(new Bundle {
         val a = Input(Bool())
         val b = Output(Bool())
       })
@@ -56,17 +55,17 @@ class GroupSpec extends ChiselFlatSpec {
     val firrtlCircuit = lower(() => new MyModule)
     firrtlCircuit.modules.collect {
       case m: fir.Module if m.name == "MyModule" =>
-        Set("doubleReg") should be (collectDeclarations(m))
+        Set("doubleReg") should be(collectDeclarations(m))
       case m: fir.Module if m.name == "DosRegisters" =>
-        Set("reg1", "reg2") should be (collectDeclarations(m))
+        Set("reg1", "reg2") should be(collectDeclarations(m))
     }
     val instances = collectInstances(firrtlCircuit, Some("MyModule")).toSet
-    Set("MyModule", "MyModule.doubleReg") should be (instances)
+    Set("MyModule", "MyModule.doubleReg") should be(instances)
   }
 
   "Module Grouping" should "not include intermediate registers" in {
     class MyModule extends Module {
-      val io = IO(new Bundle{
+      val io = IO(new Bundle {
         val a = Input(Bool())
         val b = Output(Bool())
       })
@@ -81,17 +80,17 @@ class GroupSpec extends ChiselFlatSpec {
     val firrtlCircuit = lower(() => new MyModule)
     firrtlCircuit.modules.collect {
       case m: fir.Module if m.name == "MyModule" =>
-        Set("reg2", "doubleReg") should be (collectDeclarations(m))
+        Set("reg2", "doubleReg") should be(collectDeclarations(m))
       case m: fir.Module if m.name == "DosRegisters" =>
-        Set("reg1", "reg3") should be (collectDeclarations(m))
+        Set("reg1", "reg3") should be(collectDeclarations(m))
     }
     val instances = collectInstances(firrtlCircuit, Some("MyModule")).toSet
-    Set("MyModule", "MyModule.doubleReg") should be (instances)
+    Set("MyModule", "MyModule.doubleReg") should be(instances)
   }
 
   "Module Grouping" should "include intermediate wires" in {
     class MyModule extends Module {
-      val io = IO(new Bundle{
+      val io = IO(new Bundle {
         val a = Input(Bool())
         val b = Output(Bool())
       })
@@ -106,11 +105,11 @@ class GroupSpec extends ChiselFlatSpec {
     val firrtlCircuit = lower(() => new MyModule)
     firrtlCircuit.modules.collect {
       case m: fir.Module if m.name == "MyModule" =>
-        Set("doubleReg") should be (collectDeclarations(m))
+        Set("doubleReg") should be(collectDeclarations(m))
       case m: fir.Module if m.name == "DosRegisters" =>
-        Set("reg1", "reg3", "wire") should be (collectDeclarations(m))
+        Set("reg1", "reg3", "wire") should be(collectDeclarations(m))
     }
     val instances = collectInstances(firrtlCircuit, Some("MyModule")).toSet
-    Set("MyModule", "MyModule.doubleReg") should be (instances)
+    Set("MyModule", "MyModule.doubleReg") should be(instances)
   }
 }
diff --git a/src/test/scala/chiselTests/experimental/ModuleDataProductSpec.scala b/src/test/scala/chiselTests/experimental/ModuleDataProductSpec.scala
index 78986517..713f9d04 100644
--- a/src/test/scala/chiselTests/experimental/ModuleDataProductSpec.scala
+++ b/src/test/scala/chiselTests/experimental/ModuleDataProductSpec.scala
@@ -39,7 +39,7 @@ object ModuleDataProductSpec {
 class ModuleDataProductSpec extends ChiselFlatSpec {
   import ModuleDataProductSpec._
 
-  behavior of "DataProduct"
+  behavior.of("DataProduct")
 
   it should "work for UserModules (recursively)" in {
     val m = elaborateAndGetModule(new MyUserModule)
@@ -62,7 +62,7 @@ class ModuleDataProductSpec extends ChiselFlatSpec {
     val impl = implicitly[DataProduct[MyUserModule]]
     val set = impl.dataSet(m)
     for ((d, _) <- expected) {
-      set(d) should be (true)
+      set(d) should be(true)
     }
     val it = impl.dataIterator(m, "m")
     it.toList should contain theSameElementsAs (expected)
@@ -82,7 +82,7 @@ class ModuleDataProductSpec extends ChiselFlatSpec {
     val impl = implicitly[DataProduct[MyExtModule]]
     val set = impl.dataSet(m)
     for ((d, _) <- expected) {
-      set(d) should be (true)
+      set(d) should be(true)
     }
     val it = impl.dataIterator(m, "m")
     it.toList should contain theSameElementsAs (expected)
diff --git a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
index ffe3a37f..64aabb4b 100644
--- a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
+++ b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
@@ -63,7 +63,7 @@ class ProgrammaticPortsSpec extends ChiselFlatSpec with Utils {
   }
 
   "SuggestName collisions on ports" should "be illegal" in {
-    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+    a[ChiselException] should be thrownBy extractCause[ChiselException] {
       ChiselStage.elaborate(new Module {
         val foo = IO(UInt(8.W)).suggestName("apple")
         val bar = IO(UInt(8.W)).suggestName("apple")
diff --git a/src/test/scala/chiselTests/experimental/TraceSpec.scala b/src/test/scala/chiselTests/experimental/TraceSpec.scala
index 59548921..31ccdf9b 100644
--- a/src/test/scala/chiselTests/experimental/TraceSpec.scala
+++ b/src/test/scala/chiselTests/experimental/TraceSpec.scala
@@ -88,13 +88,17 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
           .flatMap(finalTarget(annos))
           .toSet
           .map { target: CompleteTarget =>
-            s"""public_flat_rd -module "${target.tokens.collectFirst { case OfModule(m) => m }.get}" -var "${target.tokens.collectFirst { case Ref(r) => r }.get}""""
+            s"""public_flat_rd -module "${target.tokens.collectFirst {
+              case OfModule(m) => m
+            }.get}" -var "${target.tokens.collectFirst { case Ref(r) => r }.get}""""
           }
           .mkString("\n") + "\n"
 
     def verilatorTemplate(data: Seq[Data], annos: AnnotationSeq): String = {
       val vpiNames = data.flatMap(finalTarget(annos)).map { ct =>
-        s"""TOP.${ct.circuit}.${ct.path.map { case (Instance(i), _) => i }.mkString(".")}.${ct.tokens.collectFirst { case Ref(r) => r }.get}"""
+        s"""TOP.${ct.circuit}.${ct.path.map { case (Instance(i), _) => i }.mkString(".")}.${ct.tokens.collectFirst {
+          case Ref(r) => r
+        }.get}"""
       }
       s"""
          |#include "V${topName}.h"
@@ -155,20 +159,34 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
     val verilog = testDir / s"$topName.v"
     val cpp = os.temp(dir = testDir, suffix = ".cpp", contents = verilatorTemplate(Seq(dut.m0.o.a.b), annos))
     val exe = testDir / "obj_dir" / s"V$topName"
-    os.proc("verilator", "-Wall", "--cc", "--exe", "--build", "--vpi", s"$cpp", s"$verilog", s"$config").call(stdout = os.Inherit, stderr = os.Inherit, cwd = testDir)
-    assert(os.proc(s"$exe").call(stdout = os.Inherit, stderr = os.Inherit).exitCode == 0, "verilator should exit peacefully")
+    os.proc("verilator", "-Wall", "--cc", "--exe", "--build", "--vpi", s"$cpp", s"$verilog", s"$config")
+      .call(stdout = os.Inherit, stderr = os.Inherit, cwd = testDir)
+    assert(
+      os.proc(s"$exe").call(stdout = os.Inherit, stderr = os.Inherit).exitCode == 0,
+      "verilator should exit peacefully"
+    )
   }
 
   "TraceFromCollideBundle" should "work" in {
     class CollideModule extends Module {
-      val a = IO(Input(Vec(2, new Bundle {
-        val b = Flipped(Bool())
-        val c = Vec(2, new Bundle {
-          val d = UInt(2.W)
-          val e = Flipped(UInt(3.W))
-        })
-        val c_1_e = UInt(4.W)
-      })))
+      val a = IO(
+        Input(
+          Vec(
+            2,
+            new Bundle {
+              val b = Flipped(Bool())
+              val c = Vec(
+                2,
+                new Bundle {
+                  val d = UInt(2.W)
+                  val e = Flipped(UInt(3.W))
+                }
+              )
+              val c_1_e = UInt(4.W)
+            }
+          )
+        )
+      )
       val a_0_c = IO(Output(UInt(5.W)))
       val a__0 = IO(Output(UInt(5.W)))
       a_0_c := DontCare
@@ -298,12 +316,14 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
     val (_, annos) = compile("NestedModule", () => new M)
     val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[M]
     val allTargets = finalTargetMap(annos)
-    allTargets(dut.a.toAbsoluteTarget) should be (Seq(refTarget("M", "a")))
-    allTargets(dut.b.toAbsoluteTarget) should be (Seq(
-      refTarget("M", "b_0"),
-      refTarget("M", "b_1"),
-    ))
-    allTargets(dut.b(0).toAbsoluteTarget) should be (Seq(refTarget("M", "b_0")))
-    allTargets(dut.b(1).toAbsoluteTarget) should be (Seq(refTarget("M", "b_1")))
+    allTargets(dut.a.toAbsoluteTarget) should be(Seq(refTarget("M", "a")))
+    allTargets(dut.b.toAbsoluteTarget) should be(
+      Seq(
+        refTarget("M", "b_0"),
+        refTarget("M", "b_1")
+      )
+    )
+    allTargets(dut.b(0).toAbsoluteTarget) should be(Seq(refTarget("M", "b_0")))
+    allTargets(dut.b(1).toAbsoluteTarget) should be(Seq(refTarget("M", "b_1")))
   }
 }
diff --git a/src/test/scala/chiselTests/experimental/Tuple.scala b/src/test/scala/chiselTests/experimental/Tuple.scala
index 5f897fbc..b57766e7 100644
--- a/src/test/scala/chiselTests/experimental/Tuple.scala
+++ b/src/test/scala/chiselTests/experimental/Tuple.scala
@@ -9,7 +9,7 @@ import chisel3.stage.ChiselStage
 
 class TupleSpec extends ChiselFlatSpec {
 
-  behavior of "Tuple"
+  behavior.of("Tuple")
 
   it should "enable using Tuple2 like Data" in {
     class MyModule extends Module {
@@ -20,8 +20,8 @@ class TupleSpec extends ChiselFlatSpec {
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign y = sel ? a : c;")
-    verilog should include ("assign z = sel ? b : d;")
+    verilog should include("assign y = sel ? a : c;")
+    verilog should include("assign z = sel ? b : d;")
   }
 
   it should "support nesting of tuples" in {
@@ -31,10 +31,10 @@ class TupleSpec extends ChiselFlatSpec {
       ((w, x), (y, z)) := ((a, b), (c, d))
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    chirrtl should include ("w <= a")
-    chirrtl should include ("x <= b")
-    chirrtl should include ("y <= c")
-    chirrtl should include ("z <= d")
+    chirrtl should include("w <= a")
+    chirrtl should include("x <= b")
+    chirrtl should include("y <= c")
+    chirrtl should include("z <= d")
   }
 
   it should "enable using Tuple3 like Data" in {
@@ -47,9 +47,9 @@ class TupleSpec extends ChiselFlatSpec {
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign v = sel ? a : f;")
-    verilog should include ("assign w = sel ? b : g;")
-    verilog should include ("assign x = sel ? c : h;")
+    verilog should include("assign v = sel ? a : f;")
+    verilog should include("assign w = sel ? b : g;")
+    verilog should include("assign x = sel ? c : h;")
   }
 
   it should "enable using Tuple4 like Data" in {
@@ -62,10 +62,10 @@ class TupleSpec extends ChiselFlatSpec {
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign v = sel ? a : f;")
-    verilog should include ("assign w = sel ? b : g;")
-    verilog should include ("assign x = sel ? c : h;")
-    verilog should include ("assign y = sel ? d : i;")
+    verilog should include("assign v = sel ? a : f;")
+    verilog should include("assign w = sel ? b : g;")
+    verilog should include("assign x = sel ? c : h;")
+    verilog should include("assign y = sel ? d : i;")
   }
 
   it should "enable using Tuple5 like Data" in {
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala b/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
index eba412f1..2c1d2e9e 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
@@ -5,20 +5,22 @@ package chiselTests.experimental.hierarchy
 import _root_.firrtl.annotations._
 import chisel3.experimental.{annotate, BaseModule}
 import chisel3.Data
-import chisel3.experimental.hierarchy.{Instance, Definition, Hierarchy}
+import chisel3.experimental.hierarchy.{Definition, Hierarchy, Instance}
 
 object Annotations {
   case class MarkAnnotation(target: IsMember, tag: String) extends SingleTargetAnnotation[IsMember] {
     def duplicate(n: IsMember): Annotation = this.copy(target = n)
   }
-  case class MarkChiselHierarchyAnnotation[B <: BaseModule](d: Hierarchy[B], tag: String, isAbsolute: Boolean) extends chisel3.experimental.ChiselAnnotation {
+  case class MarkChiselHierarchyAnnotation[B <: BaseModule](d: Hierarchy[B], tag: String, isAbsolute: Boolean)
+      extends chisel3.experimental.ChiselAnnotation {
     def toFirrtl = MarkAnnotation(d.toTarget, tag)
   }
-  case class MarkChiselAnnotation(d: Data, tag: String, isAbsolute: Boolean) extends chisel3.experimental.ChiselAnnotation {
-    def toFirrtl = if(isAbsolute) MarkAnnotation(d.toAbsoluteTarget, tag) else MarkAnnotation(d.toTarget, tag)
+  case class MarkChiselAnnotation(d: Data, tag: String, isAbsolute: Boolean)
+      extends chisel3.experimental.ChiselAnnotation {
+    def toFirrtl = if (isAbsolute) MarkAnnotation(d.toAbsoluteTarget, tag) else MarkAnnotation(d.toTarget, tag)
   }
-  def mark(d: Data, tag: String): Unit = annotate(MarkChiselAnnotation(d, tag, false))
-  def mark[B <: BaseModule](d: Hierarchy[B], tag: String): Unit = annotate(MarkChiselHierarchyAnnotation(d, tag, true))
-  def amark(d: Data, tag: String): Unit = annotate(MarkChiselAnnotation(d, tag, true))
+  def mark(d:                   Data, tag:         String): Unit = annotate(MarkChiselAnnotation(d, tag, false))
+  def mark[B <: BaseModule](d:  Hierarchy[B], tag: String): Unit = annotate(MarkChiselHierarchyAnnotation(d, tag, true))
+  def amark(d:                  Data, tag:         String): Unit = annotate(MarkChiselAnnotation(d, tag, true))
   def amark[B <: BaseModule](d: Hierarchy[B], tag: String): Unit = annotate(MarkChiselHierarchyAnnotation(d, tag, true))
 }
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
index f33f7869..efc81f94 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
@@ -5,7 +5,7 @@ package experimental.hierarchy
 
 import chisel3._
 import chisel3.experimental.BaseModule
-import chisel3.experimental.hierarchy.{Definition, Instance, instantiable, public}
+import chisel3.experimental.hierarchy.{instantiable, public, Definition, Instance}
 
 // TODO/Notes
 // - In backport, clock/reset are not automatically assigned. I think this is fixed in 3.5
@@ -19,7 +19,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
         val definition = Definition(new AddOne)
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOne :")
+      chirrtl.serialize should include("module AddOne :")
     }
     it("0.2: accessing internal fields through non-generated means is hard to do") {
       class Top extends Module {
@@ -29,7 +29,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
         definition.in
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOne :")
+      chirrtl.serialize should include("module AddOne :")
     }
     it("0.2: reset inference is not defaulted to Bool for definitions") {
       class Top extends Module with RequireAsyncReset {
@@ -38,21 +38,27 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
         i0.in := 0.U
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("inst i0 of HasUninferredReset")
+      chirrtl.serialize should include("inst i0 of HasUninferredReset")
     }
     it("0.3: module names of repeated definition should be sequential") {
       class Top extends Module {
-        val k = Module(new AddTwoParameterized(4, (x: Int) => Seq.tabulate(x){j =>
-          val addOneDef = Definition(new AddOneParameterized(x+j))
-          val addOne = Instance(addOneDef)
-          addOne
-        }))
+        val k = Module(
+          new AddTwoParameterized(
+            4,
+            (x: Int) =>
+              Seq.tabulate(x) { j =>
+                val addOneDef = Definition(new AddOneParameterized(x + j))
+                val addOne = Instance(addOneDef)
+                addOne
+              }
+          )
+        )
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOneParameterized :")
-      chirrtl.serialize should include ("module AddOneParameterized_1 :")
-      chirrtl.serialize should include ("module AddOneParameterized_2 :")
-      chirrtl.serialize should include ("module AddOneParameterized_3 :")
+      chirrtl.serialize should include("module AddOneParameterized :")
+      chirrtl.serialize should include("module AddOneParameterized_1 :")
+      chirrtl.serialize should include("module AddOneParameterized_2 :")
+      chirrtl.serialize should include("module AddOneParameterized_3 :")
     }
     it("0.4: multiple instantiations should have sequential names") {
       class Top extends Module {
@@ -61,22 +67,28 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
         val otherAddOne = Module(new AddOneParameterized(4))
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOneParameterized :")
-      chirrtl.serialize should include ("module AddOneParameterized_1 :")
+      chirrtl.serialize should include("module AddOneParameterized :")
+      chirrtl.serialize should include("module AddOneParameterized_1 :")
     }
     it("0.5: nested definitions should have sequential names") {
       class Top extends Module {
-        val k = Module(new AddTwoWithNested(4, (x: Int) => Seq.tabulate(x){j =>
-          val addOneDef = Definition(new AddOneWithNested(x+j))
-          val addOne = Instance(addOneDef)
-          addOne
-        }))
+        val k = Module(
+          new AddTwoWithNested(
+            4,
+            (x: Int) =>
+              Seq.tabulate(x) { j =>
+                val addOneDef = Definition(new AddOneWithNested(x + j))
+                val addOne = Instance(addOneDef)
+                addOne
+              }
+          )
+        )
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOneWithNested :")
-      chirrtl.serialize should include ("module AddOneWithNested_1 :")
-      chirrtl.serialize should include ("module AddOneWithNested_2 :")
-      chirrtl.serialize should include ("module AddOneWithNested_3 :")
+      chirrtl.serialize should include("module AddOneWithNested :")
+      chirrtl.serialize should include("module AddOneWithNested_1 :")
+      chirrtl.serialize should include("module AddOneWithNested_2 :")
+      chirrtl.serialize should include("module AddOneWithNested_3 :")
     }
   }
   describe("1: Annotations on definitions in same chisel compilation") {
@@ -179,7 +191,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       val (_, annos) = getFirrtlAndAnnos(new Top)
       annos should contain(MarkAnnotation("~Top|AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
     }
-    it("1.10: should work for targets on definition to have correct circuit name"){
+    it("1.10: should work for targets on definition to have correct circuit name") {
       class Top extends Module {
         val definition = Definition(new AddOneWithAnnotation)
       }
@@ -401,10 +413,12 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
-    it("6.1 An @instantiable Module that implements an @instantiable trait should be able to use extension methods from both") {
+    it(
+      "6.1 An @instantiable Module that implements an @instantiable trait should be able to use extension methods from both"
+    ) {
       class Top extends Module {
         val i: Definition[ModuleWithCommonIntf] = Definition(new ModuleWithCommonIntf)
         mark(i.io.in, "gotcha")
@@ -418,7 +432,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("6.2 A BlackBox that implements an @instantiable trait should be instantiable as that trait") {
@@ -434,7 +448,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("6.3 It should be possible to have Vectors of @instantiable traits mixing concrete subclasses") {
@@ -456,7 +470,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
@@ -495,10 +509,10 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- expectedLines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     ignore("7.1: should work on Aggregate Views that are mapped 1:1") {
@@ -523,7 +537,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       }
       val expectedAnnos = List(
         "~Top|MyModule>a".rt -> "in",
-        "~Top|MyModule>a.foo".rt -> "in_bar",
+        "~Top|MyModule>a.foo".rt -> "in_bar"
       )
       val expectedLines = List(
         "i.a <= foo",
@@ -532,10 +546,10 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- expectedLines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
index 996b36ee..de03b74b 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
@@ -11,7 +11,7 @@ object Examples {
   import Annotations._
   @instantiable
   class AddOne extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val innerWire = Wire(UInt(32.W))
     innerWire := in + 1.U
@@ -19,7 +19,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithAnnotation extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val innerWire = Wire(UInt(32.W))
     mark(innerWire, "innerWire")
@@ -28,7 +28,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithAbsoluteAnnotation extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val innerWire = Wire(UInt(32.W))
     amark(innerWire, "innerWire")
@@ -37,12 +37,12 @@ object Examples {
   }
   @instantiable
   class AddOneParameterized(width: Int) extends Module {
-    @public val in  = IO(Input(UInt(width.W)))
+    @public val in = IO(Input(UInt(width.W)))
     @public val out = IO(Output(UInt(width.W)))
     out := in + 1.U
   }
   class AddOneWithNested(width: Int) extends Module {
-    @public val in  = IO(Input(UInt(width.W)))
+    @public val in = IO(Input(UInt(width.W)))
     @public val out = IO(Output(UInt(width.W)))
     val addOneDef = Seq.fill(3)(Definition(new AddOne))
     out := in + 1.U
@@ -50,7 +50,7 @@ object Examples {
 
   @instantiable
   class AddTwo extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val definition = Definition(new AddOne)
     @public val i0: Instance[AddOne] = Instance(definition)
@@ -61,7 +61,7 @@ object Examples {
   }
   @instantiable
   class AddTwoMixedModules extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     val definition = Definition(new AddOne)
     @public val i0: Instance[AddOne] = Instance(definition)
@@ -71,24 +71,25 @@ object Examples {
     out := i1.out
   }
   @instantiable
-  class AddTwoParameterized(width: Int, makeParameterizedOnes: Int => Seq[Instance[AddOneParameterized]]) extends Module {
-    val in  = IO(Input(UInt(width.W)))
+  class AddTwoParameterized(width: Int, makeParameterizedOnes: Int => Seq[Instance[AddOneParameterized]])
+      extends Module {
+    val in = IO(Input(UInt(width.W)))
     val out = IO(Output(UInt(width.W)))
     val addOnes = makeParameterizedOnes(width)
     addOnes.head.in := in
     out := addOnes.last.out
-    addOnes.zip(addOnes.tail).foreach{ case (head, tail) => tail.in := head.out}
+    addOnes.zip(addOnes.tail).foreach { case (head, tail) => tail.in := head.out }
   }
   @instantiable
   class AddTwoWithNested(width: Int, makeParameterizedOnes: Int => Seq[Instance[AddOneWithNested]]) extends Module {
-    val in  = IO(Input(UInt(width.W)))
+    val in = IO(Input(UInt(width.W)))
     val out = IO(Output(UInt(width.W)))
     val addOnes = makeParameterizedOnes(width)
   }
 
   @instantiable
   class AddFour extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val definition = Definition(new AddTwoMixedModules)
     @public val i0 = Instance(definition)
@@ -111,7 +112,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithInstantiableWire extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val wireContainer = new WireContainer()
     wireContainer.innerWire := in + 1.U
@@ -123,7 +124,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithInstantiableModule extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val moduleContainer = new AddOneContainer()
     moduleContainer.i0.in := in
@@ -136,7 +137,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithInstantiableInstance extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val instanceContainer = new AddOneInstanceContainer()
     instanceContainer.i0.in := in
@@ -148,7 +149,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithInstantiableInstantiable extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val containerContainer = new AddOneContainerContainer()
     containerContainer.container.i0.in := in
@@ -157,12 +158,12 @@ object Examples {
   @instantiable
   class Viewer(val y: AddTwo, markPlease: Boolean) {
     @public val x = y
-    if(markPlease) mark(x.i0.innerWire, "first")
+    if (markPlease) mark(x.i0.innerWire, "first")
   }
   @instantiable
   class ViewerParent(val x: AddTwo, markHere: Boolean, markThere: Boolean) extends Module {
     @public val viewer = new Viewer(x, markThere)
-    if(markHere) mark(viewer.x.i0.innerWire, "second")
+    if (markHere) mark(viewer.x.i0.innerWire, "second")
   }
   @instantiable
   class MultiVal() extends Module {
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
index 94af9a8b..e6bf04c1 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
@@ -5,10 +5,9 @@ package experimental.hierarchy
 
 import chisel3._
 import chisel3.experimental.BaseModule
-import chisel3.experimental.hierarchy.{Definition, Instance, instantiable, public}
+import chisel3.experimental.hierarchy.{instantiable, public, Definition, Instance}
 import chisel3.util.{DecoupledIO, Valid}
 
-
 // TODO/Notes
 // - In backport, clock/reset are not automatically assigned. I think this is fixed in 3.5
 // - CircuitTarget for annotations on the definition are wrong - needs to be fixed.
@@ -22,7 +21,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val i0 = Instance(definition)
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("inst i0 of AddOne")
+      chirrtl.serialize should include("inst i0 of AddOne")
     }
     it("0.1: name of an instanceclone should not error") {
       class Top extends Module {
@@ -31,7 +30,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val i = i0.i0 // This should not error
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("inst i0 of AddTwo")
+      chirrtl.serialize should include("inst i0 of AddTwo")
     }
     it("0.2: accessing internal fields through non-generated means is hard to do") {
       class Top extends Module {
@@ -42,63 +41,63 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         i0.in
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("inst i0 of AddOne")
+      chirrtl.serialize should include("inst i0 of AddOne")
     }
   }
   describe("1: Annotations on instances in same chisel compilation") {
     it("1.0: should work on a single instance, annotating the instance") {
       class Top extends Module {
         val definition: Definition[AddOne] = Definition(new AddOne)
-        val i0: Instance[AddOne] = Instance(definition)
+        val i0:         Instance[AddOne] = Instance(definition)
         mark(i0, "i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOne".it, "i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOne".it, "i0"))
     }
     it("1.1: should work on a single instance, annotating an inner wire") {
       class Top extends Module {
         val definition: Definition[AddOne] = Definition(new AddOne)
-        val i0: Instance[AddOne] = Instance(definition)
+        val i0:         Instance[AddOne] = Instance(definition)
         mark(i0.innerWire, "i0.innerWire")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOne>innerWire".rt, "i0.innerWire"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOne>innerWire".rt, "i0.innerWire"))
     }
     it("1.2: should work on a two nested instances, annotating the instance") {
       class Top extends Module {
         val definition: Definition[AddTwo] = Definition(new AddTwo)
-        val i0: Instance[AddTwo] = Instance(definition)
+        val i0:         Instance[AddTwo] = Instance(definition)
         mark(i0.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddTwo/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddTwo/i0:AddOne".it, "i0.i0"))
     }
     it("1.3: should work on a two nested instances, annotating the inner wire") {
       class Top extends Module {
         val definition: Definition[AddTwo] = Definition(new AddTwo)
-        val i0: Instance[AddTwo] = Instance(definition)
+        val i0:         Instance[AddTwo] = Instance(definition)
         mark(i0.i0.innerWire, "i0.i0.innerWire")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddTwo/i0:AddOne>innerWire".rt, "i0.i0.innerWire"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddTwo/i0:AddOne>innerWire".rt, "i0.i0.innerWire"))
     }
     it("1.4: should work on a nested module in an instance, annotating the module") {
       class Top extends Module {
         val definition: Definition[AddTwoMixedModules] = Definition(new AddTwoMixedModules)
-        val i0: Instance[AddTwoMixedModules] = Instance(definition)
+        val i0:         Instance[AddTwoMixedModules] = Instance(definition)
         mark(i0.i1, "i0.i1")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddTwoMixedModules/i1:AddOne_1".it, "i0.i1"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddTwoMixedModules/i1:AddOne_1".it, "i0.i1"))
     }
     it("1.5: should work on an instantiable container, annotating a wire") {
       class Top extends Module {
         val definition: Definition[AddOneWithInstantiableWire] = Definition(new AddOneWithInstantiableWire)
-        val i0: Instance[AddOneWithInstantiableWire] = Instance(definition)
+        val i0:         Instance[AddOneWithInstantiableWire] = Instance(definition)
         mark(i0.wireContainer.innerWire, "i0.innerWire")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableWire>innerWire".rt, "i0.innerWire"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableWire>innerWire".rt, "i0.innerWire"))
     }
     it("1.6: should work on an instantiable container, annotating a module") {
       class Top extends Module {
@@ -107,7 +106,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(i0.moduleContainer.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableModule/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableModule/i0:AddOne".it, "i0.i0"))
     }
     it("1.7: should work on an instantiable container, annotating an instance") {
       class Top extends Module {
@@ -116,7 +115,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(i0.instanceContainer.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstance/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstance/i0:AddOne".it, "i0.i0"))
     }
     it("1.8: should work on an instantiable container, annotating an instantiable container's module") {
       class Top extends Module {
@@ -125,7 +124,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(i0.containerContainer.container.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
     }
     it("1.9: should work on public member which references public member of another instance") {
       class Top extends Module {
@@ -134,24 +133,24 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(i0.containerContainer.container.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
     }
-    it("1.10: should work for targets on definition to have correct circuit name"){
+    it("1.10: should work for targets on definition to have correct circuit name") {
       class Top extends Module {
         val definition = Definition(new AddOneWithAnnotation)
         val i0 = Instance(definition)
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|AddOneWithAnnotation>innerWire".rt, "innerWire"))
+      annos should contain(MarkAnnotation("~Top|AddOneWithAnnotation>innerWire".rt, "innerWire"))
     }
-    it("1.11: should work on things with type parameters"){
+    it("1.11: should work on things with type parameters") {
       class Top extends Module {
         val definition = Definition(new HasTypeParams[UInt](UInt(3.W)))
         val i0 = Instance(definition)
         mark(i0.blah, "blah")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:HasTypeParams>blah".rt, "blah"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:HasTypeParams>blah".rt, "blah"))
     }
   }
   describe("2: Annotations on designs not in the same chisel compilation") {
@@ -161,7 +160,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val parent = Instance(Definition(new ViewerParent(x, false, true)))
       }
       val (_, annos) = getFirrtlAndAnnos(new Top(first))
-      annos should contain (MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "first"))
+      annos should contain(MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "first"))
     }
     it("2.1: should work on an innerWire, marked in a different compilation, in instanced instantiable") {
       val first = elaborateAndGetModule(new AddTwo)
@@ -169,7 +168,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val parent = Instance(Definition(new ViewerParent(x, true, false)))
       }
       val (_, annos) = getFirrtlAndAnnos(new Top(first))
-      annos should contain (MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "second"))
+      annos should contain(MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "second"))
     }
     it("2.2: should work on an innerWire, marked in a different compilation, in instanced module") {
       val first = elaborateAndGetModule(new AddTwo)
@@ -178,7 +177,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(parent.viewer.x.i0.innerWire, "third")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top(first))
-      annos should contain (MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "third"))
+      annos should contain(MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "third"))
     }
   }
   describe("3: @public") {
@@ -188,7 +187,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(mv.x, "mv.x")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/mv:MultiVal>x".rt, "mv.x"))
+      annos should contain(MarkAnnotation("~Top|Top/mv:MultiVal>x".rt, "mv.x"))
     }
     it("3.1: should work on lazy vals") {
       class Top() extends Module {
@@ -196,7 +195,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(lv.x, lv.y)
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/lv:LazyVal>x".rt, "Hi"))
+      annos should contain(MarkAnnotation("~Top|Top/lv:LazyVal>x".rt, "Hi"))
     }
     it("3.2: should work on islookupables") {
       class Top() extends Module {
@@ -275,10 +274,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- lines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     ignore("3.10: should work on vals in constructor arguments") {
@@ -398,7 +397,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (_, annos) = getFirrtlAndAnnos(new Top)
       annos should contain(MarkAnnotation("~Top|Top/i:AddTwo/i1:AddOne".it, "blah"))
     }
-    it("5.6: should work for absolute targets on definition to have correct circuit name"){
+    it("5.6: should work for absolute targets on definition to have correct circuit name") {
       class Top extends Module {
         val definition = Definition(new AddOneWithAbsoluteAnnotation)
         val i0 = Instance(definition)
@@ -437,10 +436,12 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
-    it("6.1 An @instantiable Module that implements an @instantiable trait should be able to use extension methods from both") {
+    it(
+      "6.1 An @instantiable Module that implements an @instantiable trait should be able to use extension methods from both"
+    ) {
       class Top extends Module {
         val i: Instance[ModuleWithCommonIntf] = Instance(Definition(new ModuleWithCommonIntf))
         mark(i.io.in, "gotcha")
@@ -454,7 +455,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("6.2 A BlackBox that implements an @instantiable trait should be instantiable as that trait") {
@@ -469,7 +470,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("6.3 It should be possible to have Vectors of @instantiable traits mixing concrete subclasses") {
@@ -491,7 +492,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
@@ -530,10 +531,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- expectedLines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
 
@@ -578,15 +579,15 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         "bar.valid <= i.b.valid",
         "i.b.ready <= bar.ready",
         "bar.bits.fizz <= i.b.fizz",
-        "bar.bits.buzz <= i.b.buzz",
+        "bar.bits.buzz <= i.b.buzz"
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- expectedLines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
 
@@ -612,7 +613,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       }
       val expected = List(
         "~Top|Top/i:MyModule>a".rt -> "in",
-        "~Top|Top/i:MyModule>b.foo".rt -> "out_bar",
+        "~Top|Top/i:MyModule>b.foo".rt -> "out_bar"
       )
       val lines = List(
         "i.a <= foo",
@@ -621,10 +622,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- lines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
 
@@ -647,7 +648,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val expected = List(
         // Not 1:1 so will get split out
         "~Top|Top/i:MyModule>a".rt -> "i.ports",
-        "~Top|Top/i:MyModule>b".rt -> "i.ports",
+        "~Top|Top/i:MyModule>b".rt -> "i.ports"
       )
       val lines = List(
         "i.a <= foo",
@@ -656,10 +657,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- lines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
@@ -682,11 +683,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val expected = List(
         "~Top|HasCMAR/c:AggregatePortModule>io".rt -> "c.io",
         "~Top|HasCMAR/c:AggregatePortModule>io.out".rt -> "c.io.out"
-
       )
       val (_, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("8.1: it should support @public on a CMAR Record in Instances") {
@@ -706,11 +706,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val expected = List(
         "~Top|Top/i:HasCMAR/c:AggregatePortModule>io".rt -> "i.c.io",
         "~Top|Top/i:HasCMAR/c:AggregatePortModule>io.out".rt -> "i.c.io.out"
-
       )
       val (_, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
@@ -769,10 +768,12 @@ class InstanceSpec extends ChiselFunSpec with Utils {
     it("10.0: instancesOf") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddTwoMixedModules =>
         val targets = aop.Select.instancesOf[AddOne](m.toDefinition).map { i: Instance[AddOne] => i.toTarget }
-        targets should be (Seq(
-          "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
-          "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it,
-        ))
+        targets should be(
+          Seq(
+            "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
+            "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it
+          )
+        )
       })
       getFirrtlAndAnnos(new AddTwoMixedModules, Seq(aspect))
     }
@@ -781,14 +782,18 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val insts = aop.Select.instancesIn(m.toDefinition)
         val abs = insts.map { i: Instance[BaseModule] => i.toAbsoluteTarget }
         val rel = insts.map { i: Instance[BaseModule] => i.toTarget }
-        abs should be (Seq(
-          "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
-          "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it,
-        ))
-        rel should be (Seq(
-          "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
-          "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it,
-        ))
+        abs should be(
+          Seq(
+            "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
+            "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it
+          )
+        )
+        rel should be(
+          Seq(
+            "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
+            "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it
+          )
+        )
       })
       getFirrtlAndAnnos(new AddTwoMixedModules, Seq(aspect))
     }
@@ -797,48 +802,58 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val insts = aop.Select.allInstancesOf[AddOne](m.toDefinition)
         val abs = insts.map { i: Instance[AddOne] => i.in.toAbsoluteTarget }
         val rel = insts.map { i: Instance[AddOne] => i.in.toTarget }
-        rel should be (Seq(
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
-        ))
-        abs should be (Seq(
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
-        ))
+        rel should be(
+          Seq(
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt
+          )
+        )
+        abs should be(
+          Seq(
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddFour, Seq(aspect))
     }
     it("10.3: definitionsOf") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddTwoMixedModules =>
         val targets = aop.Select.definitionsOf[AddOne](m.toDefinition).map { i: Definition[AddOne] => i.in.toTarget }
-        targets should be (Seq(
-          "~AddTwoMixedModules|AddOne>in".rt,
-          "~AddTwoMixedModules|AddOne_1>in".rt,
-        ))
+        targets should be(
+          Seq(
+            "~AddTwoMixedModules|AddOne>in".rt,
+            "~AddTwoMixedModules|AddOne_1>in".rt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddTwoMixedModules, Seq(aspect))
     }
     it("10.4: definitionsIn") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddTwoMixedModules =>
         val targets = aop.Select.definitionsIn(m.toDefinition).map { i: Definition[BaseModule] => i.toTarget }
-        targets should be (Seq(
-          "~AddTwoMixedModules|AddOne".mt,
-          "~AddTwoMixedModules|AddOne_1".mt,
-        ))
+        targets should be(
+          Seq(
+            "~AddTwoMixedModules|AddOne".mt,
+            "~AddTwoMixedModules|AddOne_1".mt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddTwoMixedModules, Seq(aspect))
     }
     it("10.5: allDefinitionsOf") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddFour =>
         val targets = aop.Select.allDefinitionsOf[AddOne](m.toDefinition).map { i: Definition[AddOne] => i.in.toTarget }
-        targets should be (Seq(
-          "~AddFour|AddOne>in".rt,
-          "~AddFour|AddOne_1>in".rt,
-        ))
+        targets should be(
+          Seq(
+            "~AddFour|AddOne>in".rt,
+            "~AddFour|AddOne_1>in".rt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddFour, Seq(aspect))
     }
@@ -862,120 +877,139 @@ class InstanceSpec extends ChiselFunSpec with Utils {
     }
     it("10.9: allInstancesOf.ios") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddFour =>
-        val abs = aop.Select.allInstancesOf[AddOne](m.toDefinition).flatMap { i: Instance[AddOne] => aop.Select.ios(i).map(_.toAbsoluteTarget) }
-        val rel = aop.Select.allInstancesOf[AddOne](m.toDefinition).flatMap { i: Instance[AddOne] => aop.Select.ios(i).map(_.toTarget) }
-        abs should be (Seq(
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>clock".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>reset".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>out".rt,
-
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>clock".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>reset".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>out".rt,
-
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>clock".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>reset".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>out".rt,
-
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>clock".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>reset".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>out".rt,
-        ))
-
-        rel should be (Seq(
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>clock".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>reset".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>out".rt,
-
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>clock".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>reset".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>out".rt,
+        val abs = aop.Select.allInstancesOf[AddOne](m.toDefinition).flatMap { i: Instance[AddOne] =>
+          aop.Select.ios(i).map(_.toAbsoluteTarget)
+        }
+        val rel = aop.Select.allInstancesOf[AddOne](m.toDefinition).flatMap { i: Instance[AddOne] =>
+          aop.Select.ios(i).map(_.toTarget)
+        }
+        abs should be(
+          Seq(
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>clock".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>reset".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>out".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>clock".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>reset".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>out".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>clock".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>reset".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>out".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>clock".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>reset".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>out".rt
+          )
+        )
 
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>clock".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>reset".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>out".rt,
-             
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>clock".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>reset".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>out".rt,
-        ))
+        rel should be(
+          Seq(
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>clock".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>reset".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>out".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>clock".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>reset".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>out".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>clock".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>reset".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>out".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>clock".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>reset".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>out".rt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddFour, Seq(aspect))
     }
     it("10.10: allDefinitionsOf.ios") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddFour =>
-        val abs = aop.Select.allDefinitionsOf[AddOne](m.toDefinition).flatMap { i: Definition[AddOne] => aop.Select.ios(i).map(_.toAbsoluteTarget) }
-        val rel = aop.Select.allDefinitionsOf[AddOne](m.toDefinition).flatMap { i: Definition[AddOne] => aop.Select.ios(i).map(_.toTarget) }
-        abs should be (Seq(
-          "~AddFour|AddOne>clock".rt,
-          "~AddFour|AddOne>reset".rt,
-          "~AddFour|AddOne>in".rt,
-          "~AddFour|AddOne>out".rt,
-
-          "~AddFour|AddOne_1>clock".rt,
-          "~AddFour|AddOne_1>reset".rt,
-          "~AddFour|AddOne_1>in".rt,
-          "~AddFour|AddOne_1>out".rt,
-        ))
+        val abs = aop.Select.allDefinitionsOf[AddOne](m.toDefinition).flatMap { i: Definition[AddOne] =>
+          aop.Select.ios(i).map(_.toAbsoluteTarget)
+        }
+        val rel = aop.Select.allDefinitionsOf[AddOne](m.toDefinition).flatMap { i: Definition[AddOne] =>
+          aop.Select.ios(i).map(_.toTarget)
+        }
+        abs should be(
+          Seq(
+            "~AddFour|AddOne>clock".rt,
+            "~AddFour|AddOne>reset".rt,
+            "~AddFour|AddOne>in".rt,
+            "~AddFour|AddOne>out".rt,
+            "~AddFour|AddOne_1>clock".rt,
+            "~AddFour|AddOne_1>reset".rt,
+            "~AddFour|AddOne_1>in".rt,
+            "~AddFour|AddOne_1>out".rt
+          )
+        )
 
-        rel should be (Seq(
-          "~AddFour|AddOne>clock".rt,
-          "~AddFour|AddOne>reset".rt,
-          "~AddFour|AddOne>in".rt,
-          "~AddFour|AddOne>out".rt,
+        rel should be(
+          Seq(
+            "~AddFour|AddOne>clock".rt,
+            "~AddFour|AddOne>reset".rt,
+            "~AddFour|AddOne>in".rt,
+            "~AddFour|AddOne>out".rt,
+            "~AddFour|AddOne_1>clock".rt,
+            "~AddFour|AddOne_1>reset".rt,
+            "~AddFour|AddOne_1>in".rt,
+            "~AddFour|AddOne_1>out".rt
+          )
+        )
 
-          "~AddFour|AddOne_1>clock".rt,
-          "~AddFour|AddOne_1>reset".rt,
-          "~AddFour|AddOne_1>in".rt,
-          "~AddFour|AddOne_1>out".rt,
-        ))
-        
       })
       getFirrtlAndAnnos(new AddFour, Seq(aspect))
     }
     it("10.11 Select.instancesIn for typed BaseModules") {
       val aspect = aop.inspecting.InspectingAspect({ m: HasMultipleTypeParamsInside =>
         val targets = aop.Select.instancesIn(m.toDefinition).map { i: Instance[BaseModule] => i.toTarget }
-        targets should be (Seq(
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it,
-        ))     
+        targets should be(
+          Seq(
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it
+          )
+        )
       })
       getFirrtlAndAnnos(new HasMultipleTypeParamsInside, Seq(aspect))
     }
     it("10.12 Select.instancesOf for typed BaseModules if type is ignored") {
       val aspect = aop.inspecting.InspectingAspect({ m: HasMultipleTypeParamsInside =>
-        val targets = aop.Select.instancesOf[HasTypeParams[_]](m.toDefinition).map { i: Instance[HasTypeParams[_]] => i.toTarget }
-        targets should be (Seq(
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it,
-        ))       
+        val targets =
+          aop.Select.instancesOf[HasTypeParams[_]](m.toDefinition).map { i: Instance[HasTypeParams[_]] => i.toTarget }
+        targets should be(
+          Seq(
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it
+          )
+        )
       })
       getFirrtlAndAnnos(new HasMultipleTypeParamsInside, Seq(aspect))
     }
-    it("10.13 Select.instancesOf for typed BaseModules even type is specified wrongly (should be ignored, even though we wish it weren't)") {
+    it(
+      "10.13 Select.instancesOf for typed BaseModules even type is specified wrongly (should be ignored, even though we wish it weren't)"
+    ) {
       val aspect = aop.inspecting.InspectingAspect({ m: HasMultipleTypeParamsInside =>
-        val targets = aop.Select.instancesOf[HasTypeParams[SInt]](m.toDefinition).map { i: Instance[HasTypeParams[_]] => i.toTarget }
-        targets should be (Seq(
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
-          "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it,
-        ))       
+        val targets = aop.Select.instancesOf[HasTypeParams[SInt]](m.toDefinition).map { i: Instance[HasTypeParams[_]] =>
+          i.toTarget
+        }
+        targets should be(
+          Seq(
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it
+          )
+        )
       })
-      getFirrtlAndAnnos(new HasMultipleTypeParamsInside, Seq(aspect)) 
+      getFirrtlAndAnnos(new HasMultipleTypeParamsInside, Seq(aspect))
     }
   }
 }