diff options
| author | Jack Koenig | 2022-01-10 10:39:52 -0800 |
|---|---|---|
| committer | Jack Koenig | 2022-01-10 15:53:55 -0800 |
| commit | 3131c0daad41dea78bede4517669e376c41a325a (patch) | |
| tree | 55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala | |
| parent | dd36f97a82746cec0b25b94651581fe799e24579 (diff) | |
Apply scalafmt
Command:
sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala b/src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala index 3f149f75..4704a942 100644 --- a/src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala +++ b/src/test/scala/chiselTests/experimental/DataViewIntegrationSpec.scala @@ -5,7 +5,7 @@ package chiselTests.experimental import chisel3._ import chisel3.experimental.{BaseModule, ExtModule} import chisel3.experimental.dataview._ -import chisel3.util.{Decoupled, DecoupledIO, Queue, QueueIO, log2Ceil} +import chisel3.util.{log2Ceil, Decoupled, DecoupledIO, Queue, QueueIO} import chiselTests.ChiselFlatSpec import firrtl.transforms.DontTouchAnnotation @@ -52,6 +52,6 @@ class DataViewIntegrationSpec extends ChiselFlatSpec { "Users" should "be able to view and annotate Modules" in { val (_, annos) = getFirrtlAndAnnos(new MyModule) val ts = annos.collect { case DontTouchAnnotation(t) => t.serialize } - ts should equal (Seq("~MyModule|Queue>enq_ptr_value")) + ts should equal(Seq("~MyModule|Queue>enq_ptr_value")) } } |
