summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/When.scala
diff options
context:
space:
mode:
authorJim Lawson2016-07-20 17:08:55 -0700
committerJim Lawson2016-07-20 17:08:55 -0700
commit1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 (patch)
tree1cea032150aae31fdf7cb995b26724be4b0ceb38 /src/test/scala/chiselTests/When.scala
parent2dce378deda1cc33833eb378c89a1c5415817bae (diff)
More literal/width rangling.
Diffstat (limited to 'src/test/scala/chiselTests/When.scala')
-rw-r--r--src/test/scala/chiselTests/When.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 58aa43e7..2f5c49e4 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -12,7 +12,7 @@ class WhenTester() extends BasicTester {
val cnt = Counter(4)
when(Bool(true)) { cnt.inc() }
- val out = Wire(UInt(width=3))
+ val out = Wire(UInt.width(3))
when(cnt.value === UInt.Lit(0)) {
out := UInt.Lit(1)
} .elsewhen (cnt.value === UInt.Lit(1)) {
@@ -34,7 +34,7 @@ class OverlappedWhenTester() extends BasicTester {
val cnt = Counter(4)
when(Bool(true)) { cnt.inc() }
- val out = Wire(UInt(width=3))
+ val out = Wire(UInt.width(3))
when(cnt.value <= UInt.Lit(0)) {
out := UInt.Lit(1)
} .elsewhen (cnt.value <= UInt.Lit(1)) {