From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 17:08:55 -0700
Subject: More literal/width rangling.

---
 src/test/scala/chiselTests/When.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/chiselTests/When.scala')

diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 58aa43e7..2f5c49e4 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -12,7 +12,7 @@ class WhenTester() extends BasicTester {
   val cnt = Counter(4)
   when(Bool(true)) { cnt.inc() }
 
-  val out = Wire(UInt(width=3))
+  val out = Wire(UInt.width(3))
   when(cnt.value === UInt.Lit(0)) {
     out := UInt.Lit(1)
   } .elsewhen (cnt.value === UInt.Lit(1)) {
@@ -34,7 +34,7 @@ class OverlappedWhenTester() extends BasicTester {
   val cnt = Counter(4)
   when(Bool(true)) { cnt.inc() }
 
-  val out = Wire(UInt(width=3))
+  val out = Wire(UInt.width(3))
   when(cnt.value <= UInt.Lit(0)) {
     out := UInt.Lit(1)
   } .elsewhen (cnt.value <= UInt.Lit(1)) {
-- 
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