diff options
| author | Andrew Waterman | 2017-02-24 00:33:42 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-03-08 11:27:04 -0600 |
| commit | 5f846792824cdb467691d929d64de117bb3cffcb (patch) | |
| tree | eb4abdb7c3079ab6188300d081bea17a8e9c83c7 /src/test/scala/chiselTests/Tbl.scala | |
| parent | 94c507b1dab33b7b5f4ca864d6b97cbd1682fc7f (diff) | |
Avoid log2Up in tests
Diffstat (limited to 'src/test/scala/chiselTests/Tbl.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Tbl.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 03b08709..b938361f 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -11,8 +11,8 @@ import chisel3.util._ class Tbl(w: Int, n: Int) extends Module { val io = IO(new Bundle { - val wi = Input(UInt(log2Up(n).W)) - val ri = Input(UInt(log2Up(n).W)) + val wi = Input(UInt(log2Ceil(n).W)) + val ri = Input(UInt(log2Ceil(n).W)) val we = Input(Bool()) val d = Input(UInt(w.W)) val o = Output(UInt(w.W)) |