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authorSchuyler Eldridge2020-06-22 20:34:46 -0400
committerGitHub2020-06-22 20:34:46 -0400
commit9f44b593efe4830aeb56d17f5ed59277a74832f8 (patch)
treeac43010dd7fc2a14303497f95e12f2a40bb16d0e /src/test/scala/chiselTests/SwitchSpec.scala
parentd099d01ae6b11d8befdf7b32ab74c3167a552984 (diff)
parentb5e59895e13550006fd8e951b7e9483de00f82dd (diff)
Merge pull request #1481 from freechipsproject/driver-deprecations
Remove Deprecated Usages of chisel3.Driver, CircuitForm
Diffstat (limited to 'src/test/scala/chiselTests/SwitchSpec.scala')
-rw-r--r--src/test/scala/chiselTests/SwitchSpec.scala11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala
index 2991a928..79849c76 100644
--- a/src/test/scala/chiselTests/SwitchSpec.scala
+++ b/src/test/scala/chiselTests/SwitchSpec.scala
@@ -3,12 +3,13 @@
package chiselTests
import chisel3._
+import chisel3.stage.ChiselStage
import chisel3.util._
-class SwitchSpec extends ChiselFlatSpec {
+class SwitchSpec extends ChiselFlatSpec with Utils {
"switch" should "require literal conditions" in {
- a [java.lang.IllegalArgumentException] should be thrownBy {
- elaborate(new Module {
+ a [java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
+ ChiselStage.elaborate(new Module {
val io = IO(new Bundle {})
val state = RegInit(0.U)
val wire = WireDefault(0.U)
@@ -19,8 +20,8 @@ class SwitchSpec extends ChiselFlatSpec {
}
}
it should "require mutually exclusive conditions" in {
- a [java.lang.IllegalArgumentException] should be thrownBy {
- elaborate(new Module {
+ a [java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
+ ChiselStage.elaborate(new Module {
val io = IO(new Bundle {})
val state = RegInit(0.U)
switch (state) {