From 6e03f63d525aac0bdf4a59b6fe66a0b4d5a3a25a Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 16 Jun 2020 11:59:15 -0400 Subject: Use ChiselStage in Tests This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge --- src/test/scala/chiselTests/SwitchSpec.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'src/test/scala/chiselTests/SwitchSpec.scala') diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala index 2991a928..79849c76 100644 --- a/src/test/scala/chiselTests/SwitchSpec.scala +++ b/src/test/scala/chiselTests/SwitchSpec.scala @@ -3,12 +3,13 @@ package chiselTests import chisel3._ +import chisel3.stage.ChiselStage import chisel3.util._ -class SwitchSpec extends ChiselFlatSpec { +class SwitchSpec extends ChiselFlatSpec with Utils { "switch" should "require literal conditions" in { - a [java.lang.IllegalArgumentException] should be thrownBy { - elaborate(new Module { + a [java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] { + ChiselStage.elaborate(new Module { val io = IO(new Bundle {}) val state = RegInit(0.U) val wire = WireDefault(0.U) @@ -19,8 +20,8 @@ class SwitchSpec extends ChiselFlatSpec { } } it should "require mutually exclusive conditions" in { - a [java.lang.IllegalArgumentException] should be thrownBy { - elaborate(new Module { + a [java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] { + ChiselStage.elaborate(new Module { val io = IO(new Bundle {}) val state = RegInit(0.U) switch (state) { -- cgit v1.2.3