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authorJim Lawson2016-10-06 08:57:10 -0700
committerJim Lawson2016-10-06 08:57:10 -0700
commit82625071405672eb4a19363d6f73f359ac28a7f5 (patch)
treedee5beff0e7333fa86c1cdcdb79c0d111114b8c9 /src/test/scala/chiselTests/Stack.scala
parentb7c6e0d1a2098b545938a5a8dfce2b1d9294532f (diff)
parent7de30c2b893a3f24d43f2e131557430eb64f6bc8 (diff)
Merge branch 'master' into tobits-deprecation
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
-rw-r--r--src/test/scala/chiselTests/Stack.scala21
1 files changed, 12 insertions, 9 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ac799c8a..a72af928 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -1,19 +1,22 @@
// See LICENSE for license details.
package chiselTests
+
import scala.collection.mutable.Stack
-import Chisel._
+
+import chisel3._
+import chisel3.util._
class ChiselStack(val depth: Int) extends Module {
- val io = new Bundle {
- val push = Bool(INPUT)
- val pop = Bool(INPUT)
- val en = Bool(INPUT)
- val dataIn = UInt(INPUT, 32)
- val dataOut = UInt(OUTPUT, 32)
- }
+ val io = IO(new Bundle {
+ val push = Input(Bool())
+ val pop = Input(Bool())
+ val en = Input(Bool())
+ val dataIn = Input(UInt.width(32))
+ val dataOut = Output(UInt.width(32))
+ })
- val stack_mem = Mem(depth, UInt(width = 32))
+ val stack_mem = Mem(depth, UInt.width(32))
val sp = Reg(init = UInt(0, width = log2Up(depth + 1)))
val out = Reg(init = UInt(0, width = 32))