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| author | Jim Lawson | 2016-07-20 17:08:55 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-20 17:08:55 -0700 |
| commit | 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 (patch) | |
| tree | 1cea032150aae31fdf7cb995b26724be4b0ceb38 /src/test/scala/chiselTests/Stack.scala | |
| parent | 2dce378deda1cc33833eb378c89a1c5415817bae (diff) | |
More literal/width rangling.
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Stack.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 440228c9..0c84e62a 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -16,7 +16,7 @@ class ChiselStack(val depth: Int) extends Module { val dataOut = Output(UInt.width(32)) }) - val stack_mem = Mem(depth, UInt(width = 32)) + val stack_mem = Mem(depth, UInt.width(32)) val sp = Reg(init = UInt(0, width = log2Up(depth + 1))) val out = Reg(init = UInt(0, width = 32)) |